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74AUP1T57GW Fiches technique(PDF) 3 Page - NXP Semiconductors

No de pièce 74AUP1T57GW
Description  Low-power configurable gate with voltage-level translator
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Fabricant  NXP [NXP Semiconductors]
Site Internet  http://www.nxp.com
Logo NXP - NXP Semiconductors

74AUP1T57GW Fiches technique(HTML) 3 Page - NXP Semiconductors

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74AUP1T57_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 3 August 2009
3 of 17
NXP Semiconductors
74AUP1T57
Low-power configurable gate with voltage-level translator
6.
Pinning information
6.1 Pinning
6.2 Pin description
7.
Functional description
[1]
H = HIGH voltage level;
L = LOW voltage level.
Fig 2.
Pin configuration SOT363
(SC-88)
Fig 3.
Pin configuration SOT886
(XSON6)
Fig 4.
Pin configuration SOT891
(XSON6)
74AUP1T57
BC
GND
AY
001aah472
1
2
3
6
VCC
5
4
74AUP1T57
GND
001aah471
B
A
VCC
C
Y
Transparent top view
2
3
1
5
4
6
74AUP1T57
GND
001aah473
B
A
VCC
C
Y
Transparent top view
2
3
1
5
4
6
Table 3.
Pin description
Symbol
Pin
Description
B
1
data input
GND
2
ground (0 V)
A
3
data input
Y
4
data output
VCC
5
supply voltage
C
6
data input
Table 4.
Function table[1]
Input
Output
C
B
A
Y
LLLH
LLH
L
LH
LH
L
HHL
H
LLL
HL
HL
HHL
H
HHHH


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