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74AUP1G885GD Fiches technique(PDF) 2 Page - NXP Semiconductors |
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74AUP1G885GD Fiches technique(HTML) 2 Page - NXP Semiconductors |
2 / 19 page 74AUP1G885_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 26 June 2009 2 of 19 NXP Semiconductors 74AUP1G885 Low-power dual function gate 3. Ordering information 4. Marking [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1G885DC −40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 74AUP1G885GT −40 °C to +125 °C XSON8 plastic extremely thin small outline package; no leads; 8 terminals; body 1 × 1.95 × 0.5 mm SOT833-1 74AUP1G885GD −40 °C to +125 °C XSON8U plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 3 × 2 × 0.5 mm SOT996-2 74AUP1G885GM −40 °C to +125 °C XQFN8U plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 × 1.6 × 0.5 mm SOT902-1 Table 2. Marking codes Type number Marking code[1] 74AUP1G885DC pS8 74AUP1G885GT pS8 74AUP1G885GD pS8 74AUP1G885GM pS8 Fig 1. Logic diagram 001aah898 A 2Y 1Y B C |
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