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74AUP1G175GF Fiches technique(PDF) 1 Page - NXP Semiconductors

No de pièce 74AUP1G175GF
Description  Low-power D-type flip-flop with reset; positive-edge trigger
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Fabricant  NXP [NXP Semiconductors]
Site Internet  http://www.nxp.com
Logo NXP - NXP Semiconductors

74AUP1G175GF Fiches technique(HTML) 1 Page - NXP Semiconductors

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1.
General description
The 74AUP1G175 provides a low-power, low-voltage positive-edge triggered D-type
flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q
output.The master reset (MR) is an asynchronous active LOW input and operates
independently of the clock input. Information on the data input is transferred to the
Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable
one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low
static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2.
Features
I Wide supply voltage range from 0.8 V to 3.6 V
I High noise immunity
I Complies with JEDEC standards:
N JESD8-12 (0.8 V to 1.3 V)
N JESD8-11 (0.9 V to 1.65 V)
N JESD8-7 (1.2 V to 1.95 V)
N JESD8-5 (1.8 V to 2.7 V)
N JESD8-B (2.7 V to 3.6 V)
I ESD protection:
N HBM JESD22-A114E Class 3A exceeds 5000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Low static power consumption; ICC = 0.9 µA (maximum)
I Latch-up performance exceeds 100 mA per JESD 78 Class II
I Inputs accept voltages up to 3.6 V
I Low noise overshoot and undershoot < 10 % of VCC
I IOFF circuitry provides partial Power-down mode operation
I Multiple package options
I Specified from −40 °Cto+85 °C and −40 °C to +125 °C
74AUP1G175
Low-power D-type flip-flop with reset; positive-edge trigger
Rev. 02 — 28 February 2008
Product data sheet


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