1.

General description

The 74ALVCH16374 is 16-bit edge-triggered flip-flop featuring separate D-type inputs for

each flip-flop and 3-state outputs for bus oriented applications.

Incorporates bus hold data inputs which eliminate the need for external pull-up or

pull-down resistors to hold unused inputs.

The 74ALVCH16374 consists of 2 sections of eight edge-triggered flip-flops. A clock (CP)

input and an output enable (OE) are provided per 8-bit section.

The flip-flops will store the state of their individual D-inputs that meet the set-up and hold

time requirements on the LOW-to-HIGH CP transition.

When OE is LOW, the contents of the flip-flops are available at the outputs. When OE is

HIGH, the outputs go the high-impedance OFF-state. Operation of the OE input does not

affect the state of the flip-flops.

2.

Features and benefits

Wide supply voltage range from 1.2 V to 3.6 V

Complies with JEDEC standard JESD8-B

CMOS low power consumption

MULTIBYTE flow-through standard pin-out architecture

Direct interface with TTL levels

All data inputs have bus hold

Output drive capability 50

Ω transmission lines at 85 °C

Current drive

±24 mA at V

74ALVCH16374

2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

Rev. 03 — 27 April 2010

Product data sheet