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74ABT16240ADGG Fiches technique(PDF) 9 Page - NXP Semiconductors |
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74ABT16240ADGG Fiches technique(HTML) 9 Page - NXP Semiconductors |
9 / 14 page 74ABT16240A_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 25 March 2009 9 of 14 NXP Semiconductors 74ABT16240A 16-bit inverting buffer/line driver; 3-state 12. Test information VM = 1.5 V. a. Input pulse definition Test data is given in Table 8. Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. b. Test circuit for 3-state outputs Fig 6. Load circuitry for switching times 001aac221 VM VM tW tW 10 % 90 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % 10 % tf tr tr tf 001aac764 VCC VI VO VEXT RT RL RL CL PULSE GENERATOR DUT Table 8. Test data Input Load VEXT VI fi tW tr, tf CL RL tPHZ, tPZH tPLZ, tPZL tPLH, tPHL 3.0 V 1 MHz 500 ns 2.5 ns 50 pF 500 Ω open 7.0 V open |
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