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SS6341CSTB Fiches technique(PDF) 9 Page - Silicon Standard Corp.

No de pièce SS6341CSTB
Description  High Performance, Triple-Output, Auto-Tracking Combo Controller
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Fabricant  SSC [Silicon Standard Corp.]
Site Internet  http://www.siliconstandard.com
Logo SSC - Silicon Standard Corp.

SS6341CSTB Fiches technique(HTML) 9 Page - Silicon Standard Corp.

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SS6341
width continues until the output reaches sufficient voltage
to transfer control to the input reference
clamp.
Each linear output (VOUT2 and VOUT3) initially follows a
ramp. When each output reaches sufficient voltage, the
input reference clamp slows the rate of output voltage
rise.
Over-Current Protection
All outputs are protected against excessive over-current.
The
PWM
controller
uses
the
upper
MOSFET’s
on-resistance,
RDS(ON)
to
monitor
the
current
for
protection against shorted outputs. Both the linear
regulator and controller monitor FB2 and FB3 for
under-voltage to protect against excessive current.
When the voltage across Q1 (ID x RDS(ON)) exceeds the
level (200
µA x ROCSET), this signal inhibits all outputs,
discharges the soft-start capacitor (Css) with 10
µA current
sink, and increments the counter. Css recharges and
initiates a soft-start cycle again until the counter
increments to 3. This sets the fault latch to disable all
outputs. Fig. 3 illustrates the over-current protection for
an over load on OUT1.
Should excessive current cause FB2 or FB3 to fall below
the linear under-voltage threshold, the LUV signal sets
the over-current latch if Css is fully charged. Cycling the
bias input power off then on resets the counter and the
fault latch.
The over-current function for the PWM controller will trip
at a peak inductor current (IPEAK) determined by:
I
I
R
R
PEAK
OCSET
OCSET
DS(ON)
=
×
The OC trip point varies with the MOSFET’s temperature.
To avoid over-current tripping in the normal operating
load range, determine the ROCSET resistor from the
equation above with:
1. The maximum RDS(ON) at the highest junction.
2. The minimum IOCSET from the specification table.
3. Ensure IPEAK > IOUT(MAX) + (inductor ripple current) /2.
Shutdown
Compatible with TTL logic levels, holding the SD (pin3)
pin low will activate the controller. If connecting a resistor
to ground, make sure the resistor is less than 4.7K
Ω for
normal operation.
Layout Considerations
Any inductance in the switched current path generates a
large voltage spike during the switching interval. The
voltage spikes can degrade efficiency, radiate noise into
the circuit, and lead to device over-voltage stress. Careful
component
selection
and
tight
layout
of
critical
components using short, wide metal traces minimizes
these voltage spikes.
1) A ground plane should be used. Locate the input
capacitors (CIN) close to the power switches.
Minimize the loop formed by CIN, the upper MOSFET
(Q1) and the lower MOSFET (Q2) as much as
possible. Connections should be as wide and as
short as possible to minimize loop inductance.
2) The connection between Q1, Q2 and output inductor
should be as wide and as short as practical, as this
connection has fast voltage transitions and can
easily induce EMI.
3) The output capacitor (COUT) should be located as
close to the load as possible. Minimizing the
transient load magnitude for high slew rate requires
low inductance and resistance in the circuit board.
4) The SS6341 is best placed over a quiet ground
plane area. The GND pin should be connected to the
groundside of the output capacitors. Under no
circumstances should GND be returned to a ground
inside the CIN, Q1, and Q2 loop. The GND and
PGND pins should be shorted right at the IC. This
helps to minimize internal ground disturbances in the
IC and prevents differences in ground potential from
disrupting the internal circuit operation.
5) The wiring traces from the control IC to the MOSFET
gate and source should be sized to carry a current of
1A. Locate COUT2 close to the SS6341.
6) The Vcc pin should be decoupled directly to GND by
a 1
µF ceramic capacitor; trace lengths should be as
short as possible.
Rev.2.01 6/26/2003


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