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BU4320 Fiches technique(PDF) 9 Page - Rohm

No de pièce BU4320
Description  Low Voltage Free Delay Time Setting CMOS Voltage Detector IC Series
Download  12 Pages
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Fabricant  ROHM [Rohm]
Site Internet  http://www.rohm.com
Logo ROHM - Rohm

BU4320 Fiches technique(HTML) 9 Page - Rohm

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Technical Note
9/11
BU42□□G series, BU42□□F series, BU42□□FVE series,
BU43□□G series, BU43□□F series, BU43□□FVE series
www.rohm.com
2009.11 - Rev.C
© 2009 ROHM Co., Ltd. All rights reserved.
13. Delay time (tPLH)
tPLH = τ × RCT × CCT (sec)
τ: time constant
RCT : 10MΩ (typ.) (built-in resistor)
CCT : capacitor connected CT pin.
Recommended value of CCT capacitor is over 100pF.
The reference value
(τ × RCT) ×10
6
VDET = 0.9 to 2.5V
Ta = 25°C
(min. = 5.1 × 10
6
typ.= 6.0 × 10
6
max = 6.9 × 10
6)
Ta = -25 to 125°C (min. = 3.3 × 10
6
typ. = 6.0 × 10
6
max = 8.7 × 10
6)
VDET = 2.6 to 4.8V
Ta = 25°C
(min. = 5.9 × 10
6
typ.= 6.9 × 10
6
max = 7.9 × 10
6)
Ta = -25 to 125°C (min. = 3.8 × 10
6
typ.= 6.9 × 10
6
max = 10.0 × 10
6)
14. External parameters
The recommended parameter range for CT is 100pF~0.1µF. For RL, the recommended range is 50kΩ~1MΩ. There
are many factors (board layout, etc) that can affect characteristics. Please verify and confirm using practical applications.
15. CT pin discharge
Due to the capabilities of the CT pin discharge transistor, the CT pin may not completely discharge when a short input
pulse is applied, and in this case the delay time may not be controlled. Please verify the actual operation.
16. Power on reset operation
Please note that the power on reset output varies with the Vcc rise up time. Please verify the actual operation.
17. Precautions for board inspection
Connecting low-impedance capacitors to run inspections with the board may produce stress on the IC.
Therefore, be certain to use proper discharge procedure before each process of the test operation.
To prevent electrostatic accumulation and discharge in the assembly process, thoroughly ground yourself and any
equipment that could sustain ESD damage, and continue observing ESD-prevention procedures in all handing, transfer
and storage operations. Before attempting to connect components to the test setup, make certain that the power supply is
OFF. Likewise, be sure the power supply is OFF before removing any component connected to the test setup.
18. When the power supply, is turned on because of in certain cases, momentary Rash-current flow into the IC at the logic
unsettled, the couple capacitance, GND pattern of width and leading line must be considered.


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