BU1521GVW

Technical Note

10/15

www.rohm.com

2009.05 - Rev.A

© 2009 ROHM Co., Ltd. All rights reserved.

5.

Register access

Registers are accessed by 3 wire serial interfaces (SCSB, SCLK, SDIN, SDOUT).

Burst write/read is supported; therefore, consecutive writing is possible.



Regular write sequence

The address 8 bits and data 8 bits should be written in this order.

Both address and data have MSB first.

Fig. 7 Regular write sequence



Regular read sequence

For reading, the address of the register to be read out should be written in the SADR register (0 × 70), then SRDAT register (0 × 80) should be read

out. Both address and data have MSB first.

Fig. 8 Regular read sequence

6.

PLL

BU1521GVW has an integrated PLL to generate and output the clock for HD format from the 27 MHz pixel clock.

The PLL output frequency is selected and output is executed according to the output format only, by setting the output format to the register.

The input frequency is 27 MHz and the output frequency can be 74.25 MHz, 74.25/1.001 MHz, 148.5 MHz, or 148.5/1.001 MHz.

With 480i/576i output format, the 27 MHz input clock is output without going through the PLL.

SCSB

SCLK

01

567

01

567

Address 8bit (MSB First)

WriteData 8bit (MSB First)

0

70

7

SDIN

SCSB

SCLK

01

567

01

56

7

ReadData 8bit (MSB First)

0

7

SDOUT

0x80 (MSB First)

0

7

SDIN