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BD45281 Fiches technique(PDF) 5 Page - Rohm

No de pièce BD45281
Description  Counter Timer Built-in CMOS Voltage Detector IC
Download  10 Pages
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Fabricant  ROHM [Rohm]
Site Internet  http://www.rohm.com
Logo ROHM - Rohm

BD45281 Fiches technique(HTML) 5 Page - Rohm

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Technical Note
5/9
BD45
□□□G, BD46□□□G series
www.rohm.com
2009.05 - Rev.C
© 2009 ROHM Co., Ltd. All rights reserved.
 Reference Data
Examples of Leading (TPLH) and Falling (TPHL) Output
Part Number
tPLH[ms]
tPHL[µs]
BD45275G
50
18
BD46275G
50
18
VDD=2.2V
3.2V
VDD=3.2V
2.2V
*This data is for reference only.
The figures will vary with the application, so please confirm actual operating conditions before use.
 Explanation of Operation
For both the open drain type (Fig.15) and the CMOS output type (Fig.16), the detection and release voltages are used as
threshold voltages. When the voltage applied to the VDD pins reaches the applicable threshold voltage, the VOUT terminal
voltage switches from either “High” to “Low” or from “Low” to “High”. Because the BD45
□□□G series uses an open drain output
type, it is possible to connect a pull-up resistor to VDD or another power supply [The output “High” voltage (VOUT) in this case
becomes VDD or the voltage of the other power supply].
Fig.15 (BD45
□□□G Type Internal Block Diagram)
Fig.16 (BD46
□□□G Type Internal Block Diagram)
 Timing Waveform
Example: the following shows the relationship between the input voltages VDD, the output voltage VOUT and ER terminal
when the input power supply voltage VDD is made to sweep up and sweep down (the circuits are those in Fig. 12 and 13).
1
When the power supply is turned on, the output is unsettled from
after over the operating limit voltage (VOPL) until TPHL. There fore
it is possible that the reset signal is not outputted when the rise
time of VDD is faster than TPHL.
2
When VDD is greater than VOPL but less than the reset release
voltage (VDET +
∆VDET), the output voltages will switch to Low.
3
If VDD exceeds the reset release voltage (VDET +
∆VDET), the
counter timer start and VOUT switches from L to H.
4
When more than the high level voltage is supplied ER terminal,
VOUT comes to “L” after tPLH delay time. Therefore, a time when
ER terminal is “H” is necessary for 100µsec or more.
5
When the ER terminal switches to Low, the counter timer starts
to operate, a delay of tPLH occurs, and VOUT switches from “L” to
“H”.
6
If VDD drops below the detection voltage (VDET) when the
power supply is powered down or when there is a power supply
fluctuation, VOUT switches to L (with a delay of tPHL).
7
The potential difference between the detection voltage and the
release voltage is known as the hysteresis width (
∆VDET). The
system is designed such that the output does not flip-flop with
power supply fluctuations within this hysteresis width, preventing
malfunctions due to noise.
These time changes by the application and use it, please verify
and confirm using practical applications.
Vref
R1
R2
R3
VDD
GND
Oscillation
Circuit Counter
Timer
Q1
VOUT
VDD
Reset
ER
Q2
Q1
Vref
R1
R2
R3
VDD
GND
Oscillation
Circuit Counter
Timer
VOUT
Reset
ER
Fig.17
VDD
VDET+ΔVDET
VDET
VOPL
0V
tPHL
VOUT
tPLH
tPHL
tPLH
③ ④
VOL
VOH
VDD
tPLH
tPHL
VEH
ER


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