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DM9102DEP Fiches technique(PDF) 2 Page - Davicom Semiconductor, Inc. |
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DM9102DEP Fiches technique(HTML) 2 Page - Davicom Semiconductor, Inc. |
2 / 3 page Specifications Integrated Fast Ethernet MAC, Physical Layer and transceiver in one chip. 128 pin LQFP with CMOS process. +2.5/3.3V Power supply with +5V tolerant I/O. Comply with PCI specification 2.2. PCI bus master architecture. PCI bus burst mode data transfer. Two large independent transmission and receipt FIFO. Up to 256K bytes Boot EPROM or Flash interface. EEPROM 93C46 interface automatically supports node ID load and configuration information. Comply with IEEE 802.3u 100Base-TX and 802.3 10Base-T. Comply with IEEE 802.3u auto-negotiation protocol for automatic link type selection. Support IEEE 802.3x Full Duplex Flow Control. VLAN frame length support. IP/TCP/UDP checksum generation and checking. Zero copy supporting. Comply with ACPI and PCI Bus Power Management. Support the MII (Media Independent Interface) for an external PHY. Support Wake-On-LAN function and remote wake-up (Magic packet, Link Change and Microsoft ® wake-up frame). Support 4 Wake-On-LAN (WOL) signals (active high pulse, active low pulse, active high, active low.) Hig h per formance 100Mb p s clock genera t or and da ta recovery circuit. Digital clock re covery circuit, using advanced d i gita l algorithm to reduce jitter. Adaptive equali z ation circuit a nd Base line wa nderin g restoration circuit for 100Mbps receiver. Pr o v ides Loo pba ck mode for eas y s y s t em d i a gno s t ics . Support HP Auto-MDIX. Low power consumption modes: - Power reduced mode (cable detection) - Power down mode - Se lec t ab le T X dr ivers for 1 : 1 or 1 . 25 :1 tra n sfo r me rs fo r additional power reduction. (1.25:1 transformers for Non Auto-MDIX only). |
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