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DM9102D Fiches technique(PDF) 9 Page - Davicom Semiconductor, Inc. |
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DM9102D Fiches technique(HTML) 9 Page - Davicom Semiconductor, Inc. |
9 / 70 page Final 9 Version: DM9102D-DS-F01 May 10, 2006 37 TEST1 I TEST Mode Control 1 In normal operation, tie low to this pin. 94 WOL O Wake up signal. The DM9102D can assert this pin if it detects link status change, magic packet, or sample frame match. The default is low active pulse mode. The DM9102D also supports High/Low and Pulse/Level options from EEPROM setting. 97 X2 O Crystal feedback output This pin is used for crystal connection only. Leave this pin open if oscillator is used. 98 X1/OSC I Crystal or Oscillator Input. (25MHz±50ppm) Connect to a 25MHz Oscillator or series resonance, fundamental frequency crystal. 102 BGRES I Bandgap Voltage Reference Resistor. It connects to a 6.8KΩ1% error tolerance resistor between this pin and BGRESG pin, to provide an accurate current reference for DM9102D (10Base-T/100Base-TX Application). 116 ISOLATE# I Isolate This pin is used to isolate the DM9102D from the PCI bus. 95 VCTRL25 O Voltage 2.5V control This pin can be used to control a BJT transistor ‘s base pin to generate a stable 2.5V power in BJT’s drain pin . 5.6 Power Pins Pin No. 128LQFP Pin Name I/O Description 101 BGRESG P Bandgap Ground It is used together with the BGRES pin. 100,107,108 AGND P Analog Ground 103,104,111,112 AVDD25 P Analog Power, +2.5V 96 AVDD P Analog Power, +3.3V 8,9,15,22,28,29,35,45, 46,58,76,86,99,125 DGND P Digital Ground 82,120 DVDD25 P Digital Power, +2.5V 4,5,12,18,19,25,32,42,52, 53,61,70 DVDD P Digital Power, +3.3V |
Numéro de pièce similaire - DM9102D |
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Description similaire - DM9102D |
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