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ST8024T Fiches technique(PDF) 3 Page - Sitronix Technology Co., Ltd.

No de pièce ST8024T
Description  COM/SEG LCD Driver
Download  28 Pages
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Fabricant  SITRONIX [Sitronix Technology Co., Ltd.]
Site Internet  http://www.sitronix.com.tw
Logo SITRONIX - Sitronix Technology Co., Ltd.

ST8024T Fiches technique(HTML) 3 Page - Sitronix Technology Co., Ltd.

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ST8024T
Preliminary
Ver 0.12
Page 3/26
2008/01/24
3.
BLOCK DIAGRAM
4.
FUNCTIONAL OPERATIONS OF EACH BLOCK
BLOCK
FUNCTION
Active Control
In case of segment mode, controls the selection or non-selection of the chip. Following
an LP signal input, and after the chip selection signal is input, a selection signal is
generated internally until 240 bits of data have been read in. Once data input has been
completed, a selection signal for cascade connection is output, and the chip is
non-selected. In case of common mode, controls the input/output data of bi-directional
pins.
SP Conversion
& Data Control
In case of segment mode, keeps input data which are 2 clocks of XCK at 4-bit parallel
input mode in latch circuit, or keeps input data which are 1 clock of XCK at 8-bit parallel
input mode in latch circuit; after that they are put on the internal data bus 8 bits at a time.
Data Latch Control
In case of segment mode, selects the state of the data latch which reads in the data bus
signals. The shift direction is controlled by the control logic. For every 16 bits of data
read in, the selection signal shifts one bit based on the state of the control circuit.
Data Latch
In case of segment mode, latches the data on the data bus. The latch state of each LCD
drive output pin is controlled by the control logic and the data latch control; 240 bits of
data are read in 30 sets of 8 bits.
Line Latch/
Shift Register
In case of segment mode, all 240 bits which have been read into the data latch are
simultaneously latched at the falling edge of the LP signal, and are output to the level
shifter block. In case of common mode, shifts data from the data input pin at the falling
edge of the LP signal.
Level Shifter
The logic voltage signal is level-shifted to the LCD drive voltage level, and is output to
the driver block.
4-Level Driver
Drives the LCD drive output pins from the line latch/shift register data, and selects one of
4 levels (V0, V12, V43 or Vss) based on the S/C, FR and /DISPOFF signals.
Control Logic
Controls the operation of each block. In case of segment mode, when an LP signal has
been input, all blocks are reset and the control logic waits for the selection signal output
from the active control block. Once the selection signal has been output, operation of the
data latch and data transmission is controlled, 240 bits of data are read in, and the chip
is non-selected. In case of common mode, controls the direction of data shift.
240-BIT 4-LEVEL DRIVER
240-BIT LEVEL SHIFTER
240-BIT LINE LATCH/SHIFT REGISTER
DATA CONTROL
SP CONVERSION & DATA CONTROL
(4 to 8 or 8 to 8)
CONTROL
LOGIC
ACTIVE
CONTROL
LEVEL
SHIFTER
8 BIT
DATA
LATCH
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
VDD
VSS
VSS
V43L
V12L
V0L
Y240
Y239
Y2
Y1
VSS
V43R
V12R
V0R
FR
/DISPOFF
EIO1
EIO2
LP
XCK
L/R
MD
S/C
8
16
16
16
240
240


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