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ST8024 Fiches technique(PDF) 8 Page - Sitronix Technology Co., Ltd. |
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ST8024 Fiches technique(HTML) 8 Page - Sitronix Technology Co., Ltd. |
8 / 28 page ST8024 Ver 2.1 Page 8/28 2009/08/19 Y1 -Y240 LCD drive output pins Corresponding directly to each bit of the data latch, one level (V0, V12, V43, or VSS) is selected and output. Table of truth values is shown in "TRUTH TABLE" in Functional Operations. (Common mode) SYMBOL FUNCTION VDD Logic system power supply pin, connected to +2.5 to +5.5 V. VSS Ground pin, connected to 0 V. V0L, V0R V12L, V12R V43L, V43R Bias power supply pins for LCD drive voltage Normally use the bias voltages set by a resistor divider. Ensure that voltages are set such that VSS < V43 < V12 < V0. ViL and ViR (i = 0,12, 43) must connect to an external power supply, and supply regular voltage which is assigned by specification for each power pin. ElO1 Shift data input/output pin for bi-directional shift register Output pin when L/R is at LGND level "L', input pin when L/R is at VDD level "H". When L/R = H, ElO1 is used as input pin, it will be pulled down. When L/R = L, ElO1 is used as output pin, it won't be pulled down. Refer to section 7.2.2. EIO2 Shift data input/output pin for bi-directional shift register Input pin when L/R is at LGND level "L", output pin when L/R is at VDD level "H". When L/R = L, EIO2 is used as input pin, it will be pulled down. When L/R = H, EIO2 is used as output pin, it won't be pulled down. Refer to section 7.2.2. LP Shift clock pulse input pin for bi-directional shift register Data is shifted at the falling edge of the clock pulse. L/R Input pin for selecting the shift direction of bi-directional shift register Data is shifted from Y240 to Y1 when set to LGND level "L", and data is shifted from Y1 to Y240 when set to VDD level "H". Refer to section 7.2.2. /DISPOFF Control input pin for output of non-select level The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. When set to LGND level "L", the LCD drive output pins (Y1-Y240) are set to level LGND. When set to "L”, the contents of the shift register are reset to not reading data. When the /DISPOFF function is canceled, the driver outputs non-select level (V12 or V43), and the shift data is read at the next falling edge of the LP. At that time, if /DISPOFF removal time does not correspond to what is shown in AC characteristics, the shift data is not read correctly. Table of truth values is shown in "TRUTH TABLE" in Functional Operations. FR AC signal input pin for LCD drive waveform The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. Normally it inputs a frame inversion signal. The LCD drive output pins' output voltage levels can be set using the shift register output signal and the FR signal. Table of truth values is shown in "TRUTH TABLE" in Functional Operations. MD Mode selection pin When set to LGND level "L", single mode operation is selected; when set to VDD level "H" dual mode operation is selected. Refer to section 7.2.2. DI7 Dual mode data input pin According to the data shift direction of the data shift register, data can be input starting from the 121st bit. When the chip is used in dual mode, DI7 will be pulled down. When the chip is used in single mode, DI7 won't be pulled down. Refer to section 7.2.2. S/C Segment mode/common mode selection pin When set to LGND level "L", common mode is set. |
Numéro de pièce similaire - ST8024 |
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Description similaire - ST8024 |
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