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SL38000ZI-XXXT Fiches technique(PDF) 9 Page - SpectraLinear Inc |
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SL38000ZI-XXXT Fiches technique(HTML) 9 Page - SpectraLinear Inc |
9 / 12 page Rev 1.1, August 7, 2008 Page 9 of 12 SL38000 SDA/SCLK fall time tF - 300 - 300 ns STOP set-up time tSU;STO 4.0 - 0.6 - ns Bus free time tBUF 4.7 - 1.3 - μs Table 2. I2C-Bus Timing Specification tLOW tF tHD;STA tR tHD;DAT tSU;DAT tHIGH tF tSU;STA tHD;STA tSU;STO tBUF SDATA SCLK tR S Sr P S I2C-Bus Timing Diagram External Components & Design Considerations Typical Application Schematic TBD Comments and Recommendations Decoupling Capacitor: A decoupling capacitor of 0.1μF must be used between all VDD and VSS pins on PCB. Place the capacitor on the component side of the PCB as close to the VDD pins as possible. The PCB trace to the VDD pins and to the GND via should be kept as short as possible Do not use vias between the decoupling capacitor and the VDD pins. Series Termination Resistor: A series termination resistor is recommended if the distance between the outputs (CLKOUT or REFCLK pins) and the load is over 1 ½ inch. The nominal impedance of the all clock outputs are about 25 Ω. Use 20 Ω resistor in series with the output to terminate 50Ω trace impedance and place 20 Ω resistor as close to the SSCLK output as possible. Crystal and Crystal Load: Use only parallel resonant fundamental crystals. DO NOT USE higher overtone crystals. To meet the crystal initial accuracy specification (in ppm); the internal on-chip programmable capacitors PCin and PCout must be programmed to match the crystal load requirement. These values are given by the formula below: |
Numéro de pièce similaire - SL38000ZI-XXXT |
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Description similaire - SL38000ZI-XXXT |
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