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ADE7858 Fiches technique(PDF) 51 Page - Analog Devices

No de pièce ADE7858
Description  Poly Phase Multifunction Energy Metering IC with per Phase Active and Reactive Powers
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Site Internet  http://www.analog.com
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Preliminary Technical Data
ADE7858
Rev. PrA | Page 51 of 76
one way is to use the SS pin of the master device (i.e. the
microcontroller) as a regular I/O pin and toggle it 3 times.
Another way is to execute 3 SPI write operations to a location in
the address space that is not allocated to a specific ADE7858
register (for example 0xEBFF, where 8 bit writes can be
executed). These writes allow the SS pin to toggle 3 times. See
SPI Write Operation section for details on the write protocol
involved.
After the serial port choice is done, it needs to be locked, so the
active port remains in use until a hardware reset is executed in
PSM0 normal mode or until a power down. If I2C is the active
serial port, bit 1 (I2C_LOCK) of CONFIG2[7:0] must be set to
1 to lock it in. From this moment on, the ADE7858 ignores
spurious togglings of the SS pin and an eventual switch into
using SPI port is no longer possible. If SPI is the active serial
port, any write to CONFIG2[7:0] register locks the port. From
this moment on, a switch into using I2C port is no longer
possible.
Once locked, the serial port choice is maintained when the
ADE7858 changes PSMx, x=0, 1, 2, 3 power modes.
The functionality of the ADE7858 is accessible via several on-
chip registers. The contents of these registers can be updated or
read using the I2C or SPI interfaces. HSDC port provides the
state of up to 15 registers representing instantaneous values of
phase voltages and currents, active, reactive and apparent
powers.
I2C Compatible Interface
The ADE7858 supports a fully licensed I2C interface. The I2C
interface is implemented as a full hardware slave. SDA is the
data I/O pin, and SCL is the serial clock. These two pins are
shared with the MOSI and SCLK pins of the on-chip SPI
interface. The maximum serial clock frequency supported by
this interface is 400KHz.
The two pins used for data transfer, SDA and SCL are
configured in a Wired-AND format that allows arbitration in a
multi-master system.
The transfer sequence of an I2C system consists of a master
device initiating a transfer by generating a START condition
while the bus is idle. The master transmits the address of the
slave device and the direction of the data transfer in the initial
address transfer. If the slave acknowledges, then the data
transfer is initiated. This continues until the master issues a
STOP condition and the bus becomes idle.
I2C Write Operation
The write operation using I2C interface of the ADE7858
initiates when the master generates a START condition and
consists in one byte representing the address of the ADE7858
followed by the 16-bit address of the target register and by the
value of the register.
The most significant 7 bits of the address byte constitute the
address of the ADE7858 and they are equal to b#0111000. Bit 0
of the address byte is READ/ WRITE bit. Because this is a write
operation, it has to be cleared to 0, so the first byte of the write
operation is 0x70. After every byte is received, the ADE7858
generates an acknowledge. As registers may have 8, 16 or 32
bits, after the last bit of the register is transmitted and the
ADE7858 acknowledges the transfer, the master generates a
STOP condition. The addresses and the register content are
sent with the most significant bit first. See Figure 60 for details
of the I2C write operation.
I2C Read Operation
The read operation using the I2C interface of the ADE7858 is
done in two stages. The first stage sets the pointer to the address
of the register. The second stage reads the content of the
register.
As seen in Figure 61, the first stage initiates when the master
generates a START condition and consists in one byte
representing the address of the ADE7858 followed by the 16-bit
address of the target register. The ADE7858 acknowledges
every byte received. The address byte is similar to the address
byte of a write operation and is equal to 0x70 (See I2C Write
Operation section for details). After the last byte of the register
address has been sent and it has been acknowledged by the
ADE7858, the second stage begins with the master generating a
new START condition followed by an address byte. The most
significant 7 bits of this address byte constitute the address of
the ADE7858 and they are equal to b#0111000. Bit 0 of the
address byte is READ/ WRITE bit. Because this is a read
operation, it has to be set to 1, so the first byte of the read
operation is 0x71. After this byte is received, the ADE7858
generates an acknowledge. Then the ADE7858 sends the value
of the register and after every 8 bits are received, the master
generates an acknowledge. All the bytes are sent with the most
significant bit first. As registers may have 8, 16 or 32 bits, after
the last bit of the register is received , the master does not
acknowledge the transfer, but does generate a STOP condition.
ACK generated by
ADE7858
0
S 0 111 00 0
S
T
A
R
T
A
C
K
MS 8 bits of reg
address
slave address
A
C
K
LS 8 bits of reg
address
A
C
K
Byte3 (MS) of reg
A
C
K
Byte2 of reg
A
C
K
Byte1 of reg
S
S
T
O
P
A
C
K
15
8
7
0
31
16
15
8
7
0
A
C
K
Byte0 (LS) of reg
70


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