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FM23MLD16 Fiches technique(PDF) 4 Page - Ramtron International Corporation |
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FM23MLD16 Fiches technique(HTML) 4 Page - Ramtron International Corporation |
4 / 13 page FM23MLD16 - 512Kx16 FRAM (multi die) Rev. 1.0 Dec. 2008 Page 4 of 13 Overview The FM23MLD16 is a wordwide F-RAM memory logically organized as 524,288 x 16 and accessed using an industry standard parallel interface. All data written to the part is immediately nonvolatile with no delay. The device offers page mode operation which provides higher speed access to addresses within a page (row). An access to a different page is triggered by toggling a chip enable pin or simply by changing the upper address A(18:2). Memory Operation Users access 524,288 memory locations, each with 16 data bits through a parallel interface. The F-RAM memory is organized as 2 die each having 64K rows. Each row has 4 column locations, which allows fast access in page mode operation. Once an initial address has been latched by the falling edge of /CE1 (while CE2 high) or the rising edge of CE2 (while /CE1 low), subsequent column locations may be accessed without the need to toggle a chip enable. When either chip enable pin is deasserted, a precharge operation begins. Writes occur immediately at the end of the access with no delay. The /WE pin must be toggled for each write operation. The write data is stored in the nonvolatile memory array immediately, which is a feature unique to F-RAM called NoDelay TM writes. Read Operation A read operation begins on the falling edge of /CE1 (while CE2 high) or the rising edge of CE2 (while /CE1 low). The /CE-initiated access causes the address to be latched and starts a memory read cycle if /WE is high. Data becomes available on the bus after the access time has been satisfied. Once the address has been latched and the access completed, a new access to a random location (different row) may begin while both chip enables are still active. The minimum cycle time for random addresses is tRC. Note that unlike SRAMs, the FM23MLD16’s /CE- initiated access time is faster than the address cycle time. The FM23MLD16 will drive the data bus when /OE and at least one of the byte enables (/UB, /LB) is asserted low. The upper data byte is driven when /UB is low, and the lower data byte is driven when /LB is low. If /OE is asserted after the memory access time has been satisfied, the data bus will be driven with valid data. If /OE is asserted prior to completion of the memory access, the data bus will not be driven until valid data is available. This feature minimizes supply current in the system by eliminating transients caused by invalid data being driven onto the bus. When /OE is deasserted high, the data bus will remain in a high-Z state. Write Operation Writes occur in the FM23MLD16 in the same time interval as reads. The FM23MLD16 supports both /CE- and /WE-controlled write cycles. In both cases, the address A(18:2) is latched on the falling edge of /CE1 (while CE2 high) or the rising edge of CE2 (while /CE1 low). In a /CE-controlled write, the /WE signal is asserted prior to beginning the memory cycle. That is, /WE is low when the device is activated with a chip enable. In this case, the device begins the memory cycle as a write. The FM23MLD16 will not drive the data bus regardless of the state of /OE as long as /WE is low. Input data must be valid when the device is deselected with a chip enable. In a /WE-controlled write, the memory cycle begins when the device is activated with a chip enable. The /WE signal falls some time later. Therefore, the memory cycle begins as a read. The data bus will be driven if /OE is low, however it will hi-Z once /WE is asserted low. The /CE- and /WE-controlled write timing cases are shown in the Electrical Specifications section. In the Write Cycle Timing 2 diagram, the data bus is shown as a hi-Z condition while the chip is write-enabled and before the required setup time. Although this is drawn to look like a mid-level voltage, it is recommended that all DQ pins comply with the minimum VIH/VIL operating levels. Write access to the array begins on the falling edge of /WE after the memory cycle is initiated. The write access terminates on the deassertion of /WE, /CE1, or CE2, whichever comes first. A valid write operation requires the user to meet the access time specification prior to deasserting /WE, /CE1, or CE2. Data setup time indicates the interval during which data cannot change prior to the end of the write access (rising edge of /WE or the chip is deselected with /CE1 or CE2). Unlike other truly nonvolatile memory technologies, there is no write delay with F-RAM. Since the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. The entire memory operation occurs in a single bus cycle. Data polling, a technique used with EEPROMs to determine if a write is complete, is unnecessary. Page Mode Operation The FM23MLD16 provides the user fast access to any data within a row element. Each row has 4 column address locations. Address inputs A(1:0) define the column address to be accessed. An access can start on any column address, and other column |
Numéro de pièce similaire - FM23MLD16 |
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Description similaire - FM23MLD16 |
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