TPS53125

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SLVS947A – OCTOBER 2009 – REVISED OCTOBER 2009

DETAILED DESCRIPTION

PWM Operation

The main control loop of the TPS53125 is an adaptive on-time pulse width modulation (PWM) controller using a

proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with an internal

compensation circuit for pseudo-fixed frequency and low external component count configuration with both low

ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.

At the beginning of each cycle, the synchronous high-side MOSFET is turned on. After an internal one-shot timer

expires, this MOSFET is turned off. When the feedback voltage falls below the reference voltage, the one-shot

timer is reset and the high-side MOSFET is turned back on. The one shot is set by the converter input voltage

VIN, and the output voltage VO, to maintain a pseudo-fixed frequency over the input voltage range. An internal

ramp is added to the reference voltage to simulate output ripple, eliminating the need for ESR induced output

ripple from D-CAP mode control.

Drivers

Each channel of the TPS53125 contains two high-current resistive MOSFET gate drivers. The low-side driver is a

MOSFET whose source is connected to PGND. The high-side driver is a floating SWx referenced VBST powered

voltage during the high-side driver ON time, a capacitor is placed from SWx to VBSTx. Each driver draws

To prevent cross-conduction, there is a narrow dead-time when both high-side and low-side drivers are OFF

between each driver transition. During this time the inductor current is carried by one of the MOSFETs body

diodes.

PWM Frequency and Adaptive On-Time Control

TPS53125 employs adaptive on-time control scheme and does not have a dedicated on board oscillator.

TPS53125 runs with pseudo-constant frequency by using the input voltage and output voltage to set the on-time

one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage.

Therefore, when the duty ratio is VOUT/VIN, the frequency is constant.

5-Volt Regulator

The TPS53125 has an internal 5-V low-dropout (LDO) regulator to provide a regulated voltage for all both drivers

and the IC's internal logic. A high-quality 4.7-

μF or greater ceramic capacitor from VREG5 to GND is required to

stabilize the internal regular. An internal 10-

Ω resistor from VREG5 filters the regulator output to the IC's analog

and logic input voltage, V5FILT. An additional high-quality 1.0-

μF ceramic capacitor is required from V5FILT to

GND to filter switching noise from VREG5.

Soft Start

The TPS53125 has a programmable soft-start . When the ENx pin becomes high, 2.0-

μA current begins charging

the capacitor connected from the SS pin to GND. The internal reference for the D-CAP2™ mode control

comparator is overridden by the soft-start voltage until the soft-start voltage is greater than the internal reference

for smooth control of the output voltage during start up.

Pre-Bias Support

The TPS53125 supports pre-bias start-up without sinking current from the output capacitor. When enabled, the

low-side driver is held off until the soft-start commands a voltage higher than the pre-bias level (internal soft-start

becomes greater than feedback voltage (VFB)), then the TPS53125 slowly activates synchronous rectification by

limiting the first DRVL pulses with a narrow on-time. This limited on-time is then incremented on a cycle-by-cycle

basis until it coincides with the full 1-D off-time. This scheme prevents the initial sinking of current from the

pre-bias output, and ensure that the output voltage (VOUT) starts and ramps up smoothly into regulation and the

control loop is given time to transition from pre-biased start-up to normal mode operation.

Copyright © 2009, Texas Instruments Incorporated

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