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BUF08832AIPWPR Fiches technique(PDF) 9 Page - Texas Instruments |
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BUF08832AIPWPR Fiches technique(HTML) 9 Page - Texas Instruments |
9 / 30 page V COM OUT1 OUT2 OUT3 OUT4 GND A (1) V S (4) V SD SCL V COM-FB OUT8 OUT7 OUT6 V S (2) OUT5 GND D (1) GND A (1) BKSEL A0 SDA BUF08832 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 V S (3) (3) (3) Timing Controller 3.3V 100nF 1 F m 100nF 10 F m Source Driver (3) (3) (3) (3) V S Source Driver (3) BUF08832 www.ti.com .......................................................................................................................................... SBOS476B – AUGUST 2009 – REVISED SEPTEMBER 2009 (1) GNDA and GNDD must be connected together. (2) Pins 7 and 19 are VS. The one set of capacitors shown on pin 19 are common to both pins. (3) RC combination for the OUT pins is not recommended; see the Output Protection section. Figure 14. Typical Application Configuration (VCOM without Feedback) Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): BUF08832 |
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