© 2006 Fairchild Semiconductor Corporation

www.fairchildsemi.com

FAN21SV06 Rev. 1.0.1

3

Pin Configuration

Figure 3. MLP 5x6mm Pin Configuration (Bottom View)

Pad / Pin Definitions

Pad / Pin

Name

Description

P1, 6-12

SW

Switching Node

. Junction of high-side and low-side MOSFETs.

P2, 3-5

VIN

Power Input Voltage

. Supply voltage for the converter.

P3, 21-23

PGND

Power Ground

. Power return and Q2 source.

1

BOOT

High-Side Drive BOOT Voltage

internal synchronous bootstrap diode to recharge the capacitor on this pin to 5V.

2

VIN_Reg

Regulator Input Voltage.

Input voltage to the internal regulator. Connect to input voltage

>6.5V with 1µF bypass capacitor at the pin.

13

PGOOD

Power-Good

. An open-drain output that pulls LOW when the voltage on the FB pin is

outside the limits specified in the electrical specs. PGOOD does not assert HIGH until the

fault latch is enabled.

14

EN

ENABLE

. Enables operation when pulled to logic HIGH or left open. Toggling EN resets

the regulator after a latched-fault condition. This input has an internal pull-up. When a

latched fault occurs, EN is discharged by a current sink.

15

5V_Reg

5V Regulator Output

. Internal regulator output that provides power for the IC’s logic and

analog circuitry. This pin should be connected to AGND through a >2.2µf X5R/X7R

capacitor.

16

AGND

Analog Ground

. The signal ground for the IC. All internal control voltages are referred to

this pin. Tie this pin to the ground island/plane through the lowest impedance connection.

17

ILIM

Current Limit

limit trip threshold lower than the internal default setting.

18

Oscillator Frequency and Master/Slave Set

oscillator frequency and configures the CLK pin as an output (master). Tying this pin to

5V_Reg through a resistor configures the CLK signal as an input (slave) and establishes

the free-running oscillator frequency.

19

FB

Output Voltage Feedback

. Connect through a resistor divider to the output voltage.

20

COMP

Compensation

. Error amplifier output. Connect the external compensation network

between this pin and FB.

24

CLK

Clock

. Bi-directional signal pin, depending on master/slave configuration. When

configured as a master, this pin represents the clock output that connects directly to the

slave(s) for synchronizing with 180° phase shift.

25

RAMP

Ramp Amplitude

amplitude and also provides voltage feedforward functionality.