AD9573 datasheet(3/12 Pages) AD

No de pièce	AD9573

Description	PCI-Express Clock Generator IC, PLL Core, Dividers, Two Outputs

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AD9573

Rev. 0 | Page 3 of 12

SPECIFICATIONS

Typical (typ) is given for VDD = 3.3 V ± 10%, TA = 25°C, unless otherwise noted. Minimum (min) and maximum (max) values are given

over full VDD and TA (−40°C to +85°C) variation.

PLL CHARACTERISTICS

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

NOISE CHARACTERISTICS

PLL Noise (100 MHz Output)

@ 1 kHz

−121

dBc/Hz

@ 10 kHz

−128

dBc/Hz

@ 100 kHz

−131

dBc/Hz

@ 1 MHz

−144

dBc/Hz

@ 10 MHz

−150

dBc/Hz

@ 30 MHz

−151

dBc/Hz

PLL Noise (33.33 MHz Output)

@ 1 kHz

−131

dBc/Hz

@ 10 kHz

−137

dBc/Hz

@ 100 kHz

−140

dBc/Hz

@ 1 MHz

−150

dBc/Hz

@ 5 MHz

−151

dBc/Hz

Spurious Content

−70

dBc

PLL Figure of Merit

−217.5

dBc/Hz

CLOCK OUTPUT JITTER

Table 2.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LVDS OUTPUT ABSOLUTE TIME JITTER

RMS Jitter (100 MHz Output)

540

fsec

12 kHz to 20 MHz

CLOCK OUTPUTS

Table 3.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LVDS CLOCK OUTPUT

Termination = 100 Ω differential

Output Frequency

100

MHz

Differential Output Voltage (VOD)

500

640

700

mV

Delta VOD

25

mV

Output Offset Voltage (VOS)

1.125

1.25

1.375

V

Delta VOS

25

mV

Short-Circuit Current (ISA, ISB)

14

24

mA

Output shorted to GND

Duty Cycle

45

55

%

LVCMOS CLOCK OUTPUT

Output Frequency

33.33

MHz

Output High Voltage (VOH)

VS − 0.1

V

Sourcing 1.0 mA current

Output Low Voltage (VOL)

0.1

V

Sinking 1.0 mA current

Duty Cycle

45

55

%

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