AD9572ACPZLVD datasheet(4/20 Pages) AD

No de pièce	AD9572ACPZLVD

Description	Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs

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AD9572

Rev. 0 | Page 4 of 20

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

PLL Noise (125 MHz LVPECL Output)

@ 1 kHz

−122

dBc/Hz

33.33 MHz output disabled

@ 10 kHz

−127

dBc/Hz

33.33 MHz output disabled

@ 100 kHz

−128

dBc/Hz

33.33 MHz output disabled

@ 1 MHz

−148

dBc/Hz

33.33 MHz output disabled

@ 10 MHz

−152

dBc/Hz

33.33 MHz output disabled

@ 30 MHz

−153

dBc/Hz

33.33 MHz output disabled

PLL Noise (100 MHz LVPECL Output)

@ 1 kHz

−122

dBc/Hz

33.33 MHz output disabled

@ 10 kHz

−128

dBc/Hz

33.33 MHz output disabled

@ 100 kHz

−130

dBc/Hz

33.33 MHz output disabled

@ 1 MHz

−148

dBc/Hz

33.33 MHz output disabled

@ 10 MHz

−150

dBc/Hz

33.33 MHz output disabled

@ 30 MHz

−151

dBc/Hz

33.33 MHz output disabled

Phase Noise (33.33 MHz CMOS Output)

@ 1 kHz

−130

dBc/Hz

@ 10 kHz

−138

dBc/Hz

@ 100 kHz

−139

dBc/Hz

@ 1 MHz

−152

dBc/Hz

@ 5 MHz

−152

dBc/Hz

Phase Noise (25 MHz CMOS Output)

@ 1 kHz

−133

dBc/Hz

@ 10 kHz

−142

dBc/Hz

@ 100 kHz

−148

dBc/Hz

@ 1 MHz

−148

dBc/Hz

@ 5 MHz

−148

dBc/Hz

Spurious Content1

−70

dBc

Dominant amplitude with all outputs active

PLL Figures of Merit

−217.5

dBc/Hz

1 When the 33.33 MHz, 100 MHz, and 125 MHz clocks are enabled simultaneously, a worst-case −50 dBc spurious content might be presented on Pin 21 and Pin 22 only.

LVDS CLOCK OUTPUT JITTER

Typical (typ) is given for VS = 3.3 V, TA = 25°C, unless otherwise noted.

Table 2.

Jitter Integration

Bandwidth (Typ)

100 MHz

33M = Off/On

106.25 MHz

33M = Off/On

125 MHz

33M = Off/On

156.25 MHz

33M = Off/On

Unit

Test Conditions/Comments

12 kHz to 20 MHz

508/490

402/440

418/883

417/423

fS rms

LVDS output frequency combinations

are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×

125 MHz, 2 × 106.25 MHz

1.875 MHz to

20 MHz

178/185

fS rms

LVDS output frequency combinations

are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×

125 MHz, 2 × 106.25 MHz

637 kHz to 10 MHz

167/217

fS rms

LVDS output frequency combinations

are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×

125 MHz, 2 × 106.25 MHz

200 kHz to 10 MHz

316/308

253/776

fS rms

LVDS output frequency combinations

are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×

125 MHz, 2 × 106.25 MHz

12 kHz to 35 MHz

500 (off only)

fS rms

LVDS output frequency combinations

are 1 × 156.25 MHz, 2 × 125 MHz, 2 ×

106.25 MHz

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