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AD9267EBZ Fiches technique(PDF) 6 Page - Analog Devices |
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AD9267EBZ Fiches technique(HTML) 6 Page - Analog Devices |
6 / 24 page AD9267 Rev. 0 | Page 6 of 24 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, unless otherwise noted. Table 4. Parameter1 Conditions/Comments Temp Min Typ Max Unit CLOCK INPUT PARAMETERS Using clock multiplier Input CLK Rate Full 30 160 MSPS CLK± Period Full 6.25 33.3 ns CLK± Duty Cycle Full 40 50 60 % CLOCK INPUT PARAMETERS Direct clocking Conversion Rate Full 608 640 672 MSPS CLK± Period Full 1.48 1.5625 1.72 ns CLK± Duty Cycle Full 40 50 60 % DATA OUTPUT PARAMETERS Data Propagation Delay (tPD)2 Full 160 510 840 ps DCO± Propagation Delay (tDCO) Full -60 268 570 ps DCO± to Data Skew (tSKEW) Full 180 200 280 Ps Aperture Uncertainty (Jitter, tJ) Full 1 ps rms WAKE-UP TIME Power-Down Power 25°C 3 Μs Standby Power 25°C 9 μs Sleep Power 25°C 15 μs OUT-OF-RANGE RECOVERY TIME 25°C 100 ns SERIAL PORT INTERFACE3 SCLK Period (tSCLK) Full 40 ns SCLK Pulse Width High Time (tSHIGH) Full 16 ns SCLK Pulse Width Low Time (tSLOW) Full 16 ns SDIO to SCLK Set-Up Time (tSDS) Full 5 ns SDIO to SCLK Hold Time (tSDH) Full 2 ns CSB to SCLK Set-Up Time (tSS) Full 5 ns CSB to SCLK Hold Time (tSH) Full 2 ns 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Output propagation delay is measured from CLK± 50% transition to data D0±x to D3±x 50% transition, with 5 pF load. 3 See Figure 42 and the Serial Port Interface (SPI) section. Timing Diagram CLK± DCO± D0±x TO D3±x tPD tDCO tSKEW Figure 2. Timing Diagram |
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