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ISL6115AIBZ Fiches technique(PDF) 6 Page - Intersil Corporation |
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ISL6115AIBZ Fiches technique(HTML) 6 Page - Intersil Corporation |
6 / 10 page 6 FN6855.0 February 25, 2009 region) high rDS(ON) state. Strike a balance between the CR limit and the timing requirements to avoid periods when the external N-Channel MOSFETs may be damaged or destroyed due to excessive internal power dissipation. Refer to the MOSFET SOA information in the manufacturer’s data sheet. When driving particularly large capacitive loads a longer soft-start time to prevent current regulation upon charging and a short CR time may offer the best application solution relative to reliability and FET MTF. Physical layout of RSENSE resistor is critical to avoid the possibility of false overcurrent occurrences. Ideally, trace routing between the RSENSE resistors and the IC is as direct and as short as possible with zero current in the sense lines (see Figure 1). . CORRECT TO ISEN AND CURRENT SENSE RESISTOR INCORRECT FIGURE 1. SENSE RESISTOR PCB LAYOUT RISET Typical Performance Curves FIGURE 2. VDD BIAS CURRENT FIGURE 3. ISET SOURCE CURRENT FIGURE 4. CTIM CURRENT SOURCE FIGURE 5. CTIM OC VOLTAGE THRESHOLD 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 -40 0 25 85 125 TEMPERATURE (°C) 70 18.0 18.5 19.0 19.5 20.0 20.5 21.0 21.5 22.0 TEMPERATURE (°C) -40 0 25 85 125 70 18.8 19.0 19.2 19.4 19.6 19.8 20.0 20.2 20.4 20.6 20.8 -40 0 25 70 85 125 TEMPERATURE (°C) CTIM - 0V 1.77 1.78 1.79 1.80 1.81 1.82 -40 0 25 70 85 125 TEMPERATURE (°C) ISL6115A |
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