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UC2875N Fiches technique(PDF) 6 Page - Texas Instruments

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No de pièce UC2875N
Description  Phase Shift Resonant Controller
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

UC2875N Fiches technique(HTML) 6 Page - Texas Instruments

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CLOCKSYNC (bi-directional clock and synchronization
pin): Used as an output, this pin provides a clock signal.
As an input, this pin provides a synchronization point. In
its simplest usage, multiple devices, each with their own
local oscillator frequency, may be connected together by
the CLOCKSYNC pin and will synchronize on the fastest
oscillator. This pin may also be used to synchronize the
device to an external clock, provided the external signal
is of higher frequency than the local oscillator. A resistor
load may be needed on this pin to minimize the clock
pulse width.
E/AOUT (error amplifier output):
This is is the gain stage
for overall feedback control. Error amplifier output volt-
age levels below 1 volt will force 0° phase shift. Since the
error amplifier has a relatively low current drive capabil-
ity, the output may be overridden by driving with a suffi-
ciently low impedance source.
CS+ (current sense):The non-inverting input to the cur-
rent-fault comparator whose reference is set internally to
a fixed 2.5V (separate from VREF). When the voltage at
this pin exceeds 2.5V the current-fault latch is set, the
outputs are forced OFF and a SOFT-START cycle is initi-
ated. If a constant voltage above 2.5V is applied to this
pin the outputs are disabled from switching and held in a
low state until the CS+ pin is brought below 2.5V. The
outputs may begin switching at 0 degrees phase shift be-
fore the SOFTSTART pin begins to rise -- this condition
will not prematurely deliver power to the load.
FREQSET (oscillator frequency set pin):
A resistor and a
capacitor from FREQSET to GND will set the oscillator
frequency.
DELAYSET A-B, DELAYSET C-D (output delay control):
The user programmed current flowing from these pins to
GND set the turn-on delay for the corresponding output
pair. This delay is introduced between turn-off of one
switch and turn-on of another in the same leg of the
bridge to provide a dead time in which the resonant
switching of the external power switches takes place.
Separate delays are provided for the two half-bridges to
accommodate differences in the resonant capacitor
charging currents.
EA– (error amplifier inverting input):
This is normally con-
nected to the voltage divider resistors which sense the
power supply output voltage level.
EA+ (error amplifier non-inverting input):
This is normally
connected to a reference voltage used for comparison
with the sensed power supply output voltage level at the
EA+ pin.
GND (signal ground):All voltages are measured with re-
spect to GND. The timing capacitor, on the FREQSET
pin, any bypass capacitor on the VREF pin, bypass ca-
pacitors on VIN and the ramp capacitor, on the RAMP
pin, should be connected directly to the ground plane
near the signal ground pin.
OUTA-OUTD (outputs A-D): The outputs are 2A to-
tem-pole drivers optimized for both MOSFET gates and
level-shifting transformers. The outputs operate as pairs
with a nominal 50% duty-cycle. The A-B pair is intended
to drive one half-bridge in the external power stage and
is syncronized with the clock waveform. The C-D pair
will drive the other half-bridge with switching phase
shifted with respect to the A-B outputs.
PWRGND (power ground):VC should be bypassed with
a ceramic capacitor from the VC pin to the section of the
ground plane that is connected to PWRGND. Any re-
quired bulk reservoir capacitor should parallel this one.
Power ground and signal ground may be joined at a sin-
gle point to optimize noise rejection and minimize DC
drops.
RAMP (voltage ramp):This pin is the input to the PWM
comparator. Connect a capacitor from here to GND. A
voltage ramp is developed at this pin with a slope:
dV
dT
S e ns e Voltage
RC
SLOPE
R AMP
=
Current mode control may be achieved with a minimum
amount of external circuitry, in which case this pin pro-
vides slope compensation.
Because of the 1.3V offset between the ramp input and
the PWM comparator, the error amplifier output voltage
can not exceed the effective ramp peak voltage and duty
cycle clamping is easily achievable with appropriate val-
ues of RSLOPE and CRAMP.
SLOPE (set ramp slope/slope compensation):
A resistor
from this pin to VCC will set the current used to generate
the ramp. Connecting this resistor to the DC input line
voltage will provide voltage feed-forward.
SOFTSTART (soft start): SOFTSTART will remain at
GND as long as VIN is below the UVLO threshold.
SOFTSTART will be pulled up to about 4.8V by an inter-
nal 9
µA current source when VIN becomes valid (assum-
ing a non-fault condition). In the event of a current-fault
(CS+ voltage exceeding 2.5V), SOFTSTART will be
pulled to GND and them ramp to 4.8V. If a fault occurs
during the SOFTSTART cycle, the outputs will be imme-
diately disabled and SOFTSTART must charge fully prior
to resetting the fault latch.
For paralleled controllers, the SOFTSTART pins may be
paralled to a single capacitor, but the charge currents will
be additive.
PIN DESCRIPTIONS


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