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UC2902 Fiches technique(PDF) 5 Page - Texas Instruments |
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UC2902 Fiches technique(HTML) 5 Page - Texas Instruments |
5 / 6 page 5 UC1902 UC2902 UC3902 UNITRODE CORPORATION 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. (603) 424-2410 FAX (603) 424-3460 The values of five passive components must be deter- mined to configure the UC3902 load share controller. The output and return lines of each converter are con- nected together at the load, with current sense resistor RSENSE inserted in each negative return line. Another re- sistor, RADJ, is also inserted in each positive remote sense line. The differential share bus terminals (SHARE+ and SHARE–) of each UC3902 are connected together respectively, and the SHARE– node is also connected to the system ground. A typical application is illustrated in Figure 1. The load share controller design can be executed by fol- lowing the next few steps: Step 1. () () R V AI SENSE SHARE CSA O = • max max where ACSA is 40, the gain of the current sense amplifier. At full load, the voltage drop across the RSENSE resistor is IO (max) • RSENSE. Taking into account the gain of the current sense amplifier, the voltage at full load on the current share bus, () () VA I R SHARE CSA O SENSE max max =• • . This voltage must stay 1.5V below VCC or below 10V whichever is smaller. VSHARE represents an upper limit but the designer should select the full scale share bus voltage keeping in mind that every volt on the load share bus will increase the master controller’s supply current by approximately 100mA times the number of slave units connected parallel. Step 2. () () R V I G ADJ ADJ = max max Care must be taken to ensure that IADJ(max) is low enough to ensure that both the drive current and power dissipation are within the UC3902’s capability. For most applications, an IADJ(max) current between 5mA and 10mA is acceptable. In a typical application, a 360 Ω RG resistor from the ADJR pin to ground sets IADJ(max) to approximately 5mA. Step 3. () () () RADJ VI R I O O SENSE ADJ = • ∆ max – max max RADJ must be low enough to not affect the normal opera- tion of the converter’s voltage feedback loop. Typical RADJ values are in the 20Ω to100Ω range depending on VO, ∆VO(max) and the selected IADJ(max) value. Step 4. () C G fC R R R R AA fC C MADJ G SENSE LOAD CSA PWR = •• •• • • 2 π The share loop compensation capacitor, CC is calculated to produce the desired share loop unity gain crossover frequency, fC. The share loop error amplifier’s transconductance, GM is nominally 4.5ms. The values of the resistors are already known. Typically, fC will be set at least an order of magnitude below the converter’s closed loop bandwidth. The load share circuit is primarily intended to compensate for each converter’s initial output voltage tolerance and temperature drift, not differences in their transient response. The term APWR(fC) is the gain of the power supply measured at the desired share loop crossover frequency, fC. This gain can be measured by injecting the measurement signal between the positive output and the positive sense terminal of the power sup- ply. Step 5. R fC C C C = •• • 1 2 π A resistor in series with CC is required to boost the phase margin of the load share loop. The zero is placed at the load share loop crossover frequency, fC. When the system is powered up, the converter with the highest output voltage will tend to source the most cur- rent and take control of the share bus. The other convert- ers will increase their output voltages until their output currents are proportional to the share bus voltage minus 50mV. The converter which in functioning as the master may change due to warmup drift and differences in load and line transient response of each converter. ADDITIONAL INFORMATION Please refer to the following Unitrode topic for additional application information. [1] Application Note U-163, The UC3902 Load Share Controller and Its Performance in Distributed Power Sys- tems by Laszlo Balogh. APPLICATION INFORMATION (cont.) |
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