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UC2849 Fiches technique(PDF) 8 Page - Texas Instruments

No de pièce UC2849
Description  Secondary Side Average Current Mode Controller
Download  11 Pages
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

UC2849 Fiches technique(HTML) 8 Page - Texas Instruments

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UC1849
UC2849
UC3849
The ADJ pin voltage on the slave chips will increase forc-
ing their load currents to increase to match the master.
The AC frequency response of the voltage error amplifier
is shown in Figure 7.
Startup and Shutdown: Isolated power up can be
accomplished using the UCC1889. Application Note U-
149 is available for additional information.
The UC1849 offers several features that enhance startup
and shutdown. Soft start is accomplished by connecting
RUN to VA+ and a capacitor to ground. The resulting RC
rise time on the VA+ pin initiates a soft start. It can also
be accomplished by connecting RUN to ILIM. When RUN
is low it will command zero load current, guaranteeing a
soft start. The undervoltage lockout (UVLO) is a logical
AND of ENBL < 2.5V, SEQ > 2.5V, VCC > 8.4V and
VREF > 4.65V. The block diagram shows that the thresh-
olds are set by comparators. By placing an RC divider on
the SEQ pin, the enabling of multiple chips can be
sequenced with different RC time constants. Similarly,
different RC time constants on the ENBL pins can
sequence shutdown. The UVLO keeps the output from
switching; however the internal reference starts up with
VCC less than 8.4V. The KILL input shuts down the
switching of the chip. This can be used in conjunction
with an overvoltage comparator for overvoltage protec-
tion. In order to restart the chip after KILL has been initi-
ated, the chip must be powered down and then back up.
A pulse on the ENBL pin also accomplishes this without
actually removing voltage to the VCC pin.
Load Sharing: Load sharing is accomplished similar to
the UC1907. The sensed current for the UC1849 has an
AC component that is amplified and then averaged. The
voltage error amplifier output is the current command
signal representing the average output load current. The
ILIM pin programs the upper clamp voltage of this ampli-
fier and consequently the maximum load current. A gain
of 2 amplifier connected between the voltage error ampli-
fier output and the share amplifier input increases the
current share resolution and noise margin. The average
current is used as an input to a source only load share
buffer amplifier. The output of this amplifier is the current
share bus. The IC with the highest sensed current will
have the highest voltage on the current share bus and
consequently act as the master. The 60mV input offset
guarantees that the unit sensing the highest load current
is chosen as the master.
The adjust amplifier is used by the remaining (slave) ICs
to adjust their respective references high in order to bal-
ance each IC’s load current. The master’s ADJ pin will be
at its 1.0V clamp and connected back to the non-invert-
ing voltage error amplifier input through a high value
resistor. This requires the user to initially calculate the
control voltage with the ADJ pin at 1.0V.
VREF can be adjusted 150mV to 300mV which compen-
sates for 5% unit to unit reference mismatch and external
resistor mismatch. RADJ will typically be 10 to 30 times
larger than R1. This also attenuates the overall variation of
the ADJ clamp of 1V ±100mV by a factor of 10 to 30, con-
tributing only a 3mV to 10mV additional delta to VREF.
Refer to the UC3907 Application Note U-130 for further
information on parallel power supply load sharing.
Current Control Loop: The current sense amplifier (CSA)
is designed specifically for the task of sensing and amplify-
ing the inductor ripple current at frequencies up to 1MHz.
The CSA’s input offset voltage (VIO) is trimmed to less
than 1mV to minimize error of the average current signal.
This amplifier is not internally compensated allowing the
user to optimally choose the zero crossing bandwidth.
1
2
π RINV
· CCOMP
RINV is the input resistance at the inverting terminal CS-
CCOMP is the capacitance between CS- and CSO.
Although it is only unity gain stable for a GBW of 7MHz,
the amplifier is typically configured with a differential gain
of at least 10, allowing the amplifier to operate at 70MHz
with sufficient phase margin. A closed loop gain of 10
attenuates the output by 20.8dB.
1
11
to the inverting terminal assuring stability. The amplifier’s
gain fed back into the inverting terminal is less than unity
∅ ≈
m
Figure 7. AC Frequency Response of the Voltage
Error Amplifier
CIRCUIT BLOCK DESCRIPTION (cont.)
(3)
Frequency (0dB) =
20.8 = 20log
·


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