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UC2849 Fiches technique(PDF) 5 Page - Texas Instruments |
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UC2849 Fiches technique(HTML) 5 Page - Texas Instruments |
5 / 11 page CAO: The output of the current error amplifier which is internally clamped to 4V. It is internally connected to the inverting input of the PWM comparator. CS-, CS+: The inverting and non-inverting inputs to the current sense amplifier. This amplifier is not internally compensated so the user must compensate externally to attain the highest GBW for the application. CLKSYN: The clock and synchronization pin for the oscillator. This is a bidirectional pin that can be used to synchronize several chips to the fastest oscillator. Its input synchronization threshold is 1.4V. The CLKSYN voltage is 3.6V when the oscillator capacitor (CT) is being discharged, otherwise it is 0V. If the recommended synchronization circuit is not used, a 1k or lower value resistor from CLKSYN to GND may be needed to increase fall time on CLKSYN pin. CSO: The output of the current sense amplifier which is internally clamped to 4V. ENBL: The active low input with a 2.5V threshold enables the output to switch. SEQ and RUN are driven low when ENBL is above its 2.5V threshold. GND: The signal ground used for the voltage sense amplifier, current sense amplifier, current error amplifier, voltage reference, 2X amplifier, and share amplifier. The output sink transistor is wired directly to this pin. KILL: The active low input with a 3.0V threshold stops the output from switching. Once this function is activated RUN must be cycled low by driving KILL above 3.0V and either resetting the power to the chip (VCC) or resetting the ENBL signal. ILIM: A voltage on this pin programs the voltage error amplifier’s Voh clamp. The voltage error amplifier output represents the average output current. The Voh clamp con- sequently limits the output current. If ILIM is tied to VREF, it defaults to 3.0V. A voltage less than 3.0V connected to ILIM clamps the voltage error amplifier at this voltage and consequently limits the maximum output current. OSC: The oscillator ramp pin which has a capacitor (CT) to ground and a resistor (RDEAD) to the RDEAD pin pro- grams its maximum duty cycle by programming a mini- mum dead time. The ramp oscillates between 1.2V to 3.4V when an RDEAD resistor is used. The maximum duty cycle can be increased by connecting RDEAD to OSC which changes the oscillator ramp to vary between 0.2V and 3.5V. In order to guarantee zero duty cycle in this configuration VEE should not be connected to GND. The charge time is approximately TCHARGE = RT · CT when the RDEAD resistor is used. The dead time is approximately TDISCHARGE = 2 · RDEAD · CT. 1 TCHARGE + TDISCHARGE TCHARGE TCHARGE + TDISCHARGE The CT capacitance should be increased by approxi- mately 40pF to account for parasitic capacitance. OUT: The output of the PWM driver. It has an upper clamp of 8.5V. The peak current sink and source are 250mA. All UVLO, SEQ, ENBL, and KILL logic either enable or disable the output driver. RDEAD: The pin that programs the maximum duty cycle by connecting a resistor between it and OSC. The maxi- mum duty cycle is decreased by increasing this resistor value which increases the discharge time. The dead time, the time when the output is low, is 2 · RDEAD · CT. The CT capacitance should be increased by approxi- mately 40pF to account for parasitic capacitance. RT: This pin programs the charge time of the oscillator ramp. The charge current is VREF 2 · RT The charge time is approximately TCHARGE ≈ RT · CT when the RDEAD resistor is used. The dead time is approximately TDISCHARGE ≈ 2 · RDEAD · CT. RUN: This is an open collector logic output that signifies when the chip is operational. RUN is pulled high to VREF through an external resistor when VCC is greater than 8.4V, VREF is greater than 4.65V, SEQ is greater than 2.5V, and KILL lower than 3.0V. RUN connected to the VA+ pin and to a capacitor to ground adds an RC rise time on the VA+ pin initiating a soft start. SEQ: The sequence pin allows the sequencing of startup for multiple units. A resistor between VREF and SEQ and a capacitor between SEQ and GND creates a unique RC rise time for each unit which sequences the output start- up. SHARE:The nearly DC voltage representing the average output current. This pin is wired directly to all SHARE pins and is the load share bus. VA+, VA-: The inverting and non-inverting inputs to the voltage error amplifier. VAO: The output of the voltage error amplifier. Its Voh is clamped with the ILIM pin. 5 UC1849 UC2849 UC3849 (1) Frequency ≈ (2) Maximum Duty Cycle ≈ PIN DESCRIPTIONS (cont.) |
Numéro de pièce similaire - UC2849 |
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Description similaire - UC2849 |
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