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TSB41BA3DPFP Fiches technique(PDF) 7 Page - Texas Instruments

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No de pièce TSB41BA3DPFP
Description  IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
Download  59 Pages
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

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TSB41BA3D
www.ti.com ............................................................................................................................................... SLLS959A – DECEMBER 2008 – REVISED MARCH 2009
Table 1. Terminal Functions
TERMINAL
I/O
DESCRIPTION
PFP
NAME
TYPE
NO.
AGND
Supply
21, 40,
Analog circuit ground terminals. These terminals must be tied together to the
43, 50,
low-impedance circuit board ground plane.
61, 62
AVDD
Supply
24, 39,
Analog circuit power terminals. A combination of high-frequency decoupling capacitors near
44, 51,
each terminal is suggested, such as paralleled 0.1
µF and 0.001 µF. Lower frequency
57, 63
10-
µF filtering capacitors are also recommended. These supply terminals are separated
from the PLLVDD-CORE, PLLVDD-3.3, DVDD-CORE, and DVDD-3.3 terminals internal to
the device to provide noise isolation. The PLLVDD-3.3, AVDD, and DVDD-3.3 terminals
must be tied together with a low dc impedance connection on the circuit board.
BMODE
CMOS
74
I
Beta-mode input. This terminal determines the PHY-link interface connection protocol.
When logic-high (asserted), the PHY-link interface complies with the 1394b-2002 B
PHY-link interface. When logic-low (deasserted), the PHY-link interface complies with the
legacy 1394a-2000 standard. When using an LLC such as the 1394b-2002 TSB82AA2, this
terminal must be pulled high. When using an LLC such as the 1394a-2000 TSB12LV26,
this terminal must be tied low.
NOTE: The PHY-link interface cannot be changed between the different protocols during
operation.
CPS
CMOS
34
I
Cable-power status input. This terminal is normally connected to cable power through a
400-k
Ω resistor. This circuit drives an internal comparator that detects the presence of
cable power. This transition from cable power sensed to cable power not sensed can be
used to generate an interrupt to the LLC.
CTL0
CMOS
9
I/O
Control I/Os. These bidirectional signals control communication between the TSB41BA3D
CTL1
10
and the LLC. Bus holders are built into these terminals.
D0–D7
CMOS
11, 12,
I/O
Data I/Os. These are bidirectional data signals between the TSB82BA3 and the LLC. Bus
13, 15,
holders are built into these terminals.
16, 17,
If power management control (PMC) is selected using LCLK_PMC, then some of these
19, 20
terminals can be used for PMC. See the LCLK_PMC terminal description for more
information.
DGND
Supply
4, 14,
Digital circuit ground terminals. These terminals must be tied together to the low-impedance
38, 64,
circuit board ground plane.
72, 76
DVDD-CORE
Supply
8, 37,
Digital core circuit power terminals. A combination of high-frequency decoupling capacitors
65, 71
near each terminal is suggested, such as paralleled 0.1
µF and
0.001
µF. An additional 1-µF capacitor is required for voltage regulation. These supply
terminals are separated from the DVDD-3.3, PLLVDD-CORE, PLLVDD-3.3, and AVDD
terminals internal to the device to provide noise isolation.
DVDD-3.3
Supply
6, 18,
Digital 3.3-V circuit power terminals. A combination of high-frequency decoupling capacitors
69, 70
near each terminal is suggested, such as paralleled 0.1
µF and
0.001
µF. Lower-frequency 10-µF filtering capacitors are also recommended. The
DVDD-3.3 terminals must be tied together at a low-impedance point on the circuit board.
These supply terminals are separated from the PLLVDD-CORE, PLLVDD-3.3,
DVDD-CORE, and AVDD terminals internal to the device to provide noise isolation. The
PLLVDD-3.3, AVDD, and DVDD-3.3 terminals must be tied together with a low dc
impedance connection on the circuit board.
Copyright © 2008–2009, Texas Instruments Incorporated
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