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TPS3307-25DGNRG4 Fiches technique(PDF) 2 Page - Texas Instruments

No de pièce TPS3307-25DGNRG4
Description  TRIPLE PROCESSOR SUPERVISORS
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Site Internet  http://www.ti.com
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TPS3307-25DGNRG4 Fiches technique(HTML) 2 Page - Texas Instruments

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FUNCTION/TRUTH TABLES
TPS3307-18, TPS3307-25, TPS3307-33
SLVS199B – DECEMBER 1998 – REVISED OCTOBER 2004
An internal timer delays the return of the RESET output to the inactive state (high) to ensure proper system
reset. The delay time, td (typ) = 200ms, starts after all SENSEn inputs have risen above the threshold voltage VIT+.
When the voltage at any SENSE input drops below the threshold voltage VIT-, the RESET output becomes active
(low) again.
The TPS3307-xx family of devices incorporates a manual reset input, MR. A low level at MR causes RESET to
become active. In addition to the active-low RESET output, the TPS3307-xx family includes an active-high
RESET output.
The devices are available in either 8-pin MSOP or standard 8-pin SO packages.
The TPS3307-xx devices are characterized for operation over a temperature range of –40
°C to 85°C.
SUPPLY VOLTAGE MONITORING
NOMINAL SUPERVISED VOLTAGE
THRESHOLD VOLTAGE (TYP)
DEVICE
SENSE1
SENSE2
SENSE3
SENSE1
SENSE2
SENSE3
TPS3307-18
3.3V
1.8V
User defined
2.93V
1.68V
1.25V(1)
TPS3307-25
3.3V
2.5V
User defined
2.93V
2.25V
1.25V(1)
TPS3307-33
5V
3.3V
User defined
4.55V
2.93V
1.25V(1)
(1)
The actual sense voltage has to be adjusted by an external resistor divider according to the application requirements.
AVAILABLE OPTIONS
PACKAGED DEVICES
MARKING
CHIP FORM
PowerPAD™
TA
SMALL OUTLINE
DGN PACKAGE
(Y)
µ-SMALL OUTLINE
(D)
(DGN)
TPS3307-18D
TPS3307-18DGN
TIAAP
TPS3307-18Y
-40
°C to 85°C
TPS3307-25D
TPS3307-25DGN
TIAAQ
TPS3307-25Y
TPS3307-33D
TPS3307-33DGN
TIAAR
TPS3307-33Y
MR
SENSE1 > VIT1
SENSE2 > VIT2
SENSE3 > VIT3
RESET
RESET
L
X(1)
X(1)
X
L
H
H
0
0
0
L
H
H
0
0
1
L
H
H
0
1
0
L
H
H
0
1
1
L
H
H
1
0
0
L
H
H
1
0
1
L
H
H
1
1
0
L
H
H
1
1
1
H
L
(1)
X = Don't care
2


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