TPS2206

DUAL-SLOT PC CARD POWER-INTERFACE SWITCH

WITH RESET FOR SERIAL PCMCIA CONTROLLER

SLVS138B – MAY 1996 – REVISED JUNE 1998

8

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

Table of Timing Diagrams

FIGURE

Serial-Interface Timing

2

xVCC Propagation Delay and Rise Time With 1-

µF Load, 3.3-V Switch, VI(5V) = 5 V

3

xVCC Propagation Delay and Fall Time With 1-

µF Load, 3.3-V Switch, VI(5V) = 5 V

4

xVCC Propagation Delay and Rise Time With 150-

µF Load, 3.3-V Switch, VI(5V) = 5 V

5

xVCC Propagation Delay and Fall Time With 150-

µF Load, 3.3-V Switch, VI(5V) = 5 V

6

xVCC Propagation Delay and Rise Time With 1-

µF Load, 3.3-V Switch, VI(5V) = 0

7

xVCC Propagation Delay and Fall Time With 1-

µF Load, 3.3-V Switch, VI(5V) = 0

8

xVCC Propagation Delay and Rise Time With 150-

µF Load, 3.3-V Switch, VI(5V) = 0

9

xVCC Propagation Delay and Fall Time With 150-

µF Load, 3.3-V Switch, VI(5V) = 0

10

xVCC Propagation Delay and Rise Time With 1-

µF Load, 5-V Switch

11

xVCC Propagation Delay and Fall Time With 1-

µF Load, 5-V Switch

12

xVCC Propagation Delay and Rise Time With 150-

µF Load, 5-V Switch

13

xVCC Propagation Delay and Fall Time With 150-

µF Load, 5-V Switch

14

xVPP Propagation Delay and Rise Time With 1-

µF Load, 12-V Switch

15

xVPP Propagation Delay and Fall Time With 1-

µF Load, 12-V Switch

16

xVPP Propagation Delay and Rise Time With 150-

µF Load, 12-V Switch

17

xVPP Propagation Delay and Fall Time With 150-

µF Load, 12-V Switch

18

NOTE A: Data is clocked in on the positive leading edge of the clock. The latch should occur before the next positive leading edge of

the clock. For definition of D0 to D8, see the control logic table.

DATA

LATCH

CLOCK

D8

D7

D6

D5

D4

D3

D2

D1

D0

Figure 2. Serial-Interface Timing