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TLC5615IDGK Fiches technique(PDF) 5 Page - Texas Instruments |
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TLC5615IDGK Fiches technique(HTML) 5 Page - Texas Instruments |
5 / 18 page TLC5615C, TLC5615I 10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 digital input timing requirements (see Figure 1) PARAMETER MIN NOM MAX UNIT tsu(DS) Setup time, DIN before SCLK high 45 ns th(DH) Hold time, DIN valid after SCLK high 0 ns tsu(CSS) Setup time, CS low to SCLK high 1 ns tsu(CS1) Setup time, CS high to SCLK high 50 ns th(CSH0) Hold time, SCLK low to CS low 1 ns th(CSH1) Hold time, SCLK low to CS high 0 ns tw(CS) Pulse duration, minimum chip select pulse width high 20 ns tw(CL) Pulse duration, SCLK low 25 ns tw(CH) Pulse duration, SCLK high 25 ns output switching characteristic PARAMETER TEST CONDITIONS MIN NOM MAX UNIT tpd(DOUT) Propagation delay time, DOUT CL = 50 pF 50 ns operating characteristics over recommended operating free-air temperature range, VDD = 5 V ± 5%, Vref = 2.048 V (unless otherwise noted) analog output dynamic performance PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SR Output slew rate CL = 100 pF, TA = 25°C RL = 10 kΩ, 0.3 0.5 V/ µs ts Output settling time To 0.5 LSB, RL = 10 kΩ, CL = 100 pF, See Note 10 12.5 µs Glitch energy DIN = All 0s to all 1s 5 nV s NOTE 10: Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of 000 hex to 3FF hex or 3FF hex to 000 hex. reference input (REFIN) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Reference feedthrough REFIN = 1 Vpp at 1 kHz + 2.048 Vdc (see Note 11) –80 dB Reference input bandwidth (f–3dB) REFIN = 0.2 Vpp + 2.048 Vdc REFIN = 0.2 Vpp + 2.048 Vdc 30 kHz NOTE 11: Reference feedthrough is measured at the DAC output with an input code = 000 hex and a Vref input = 2.048 Vdc + 1 Vpp at 1 kHz. |
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Description similaire - TLC5615IDGK |
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