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TLC320AD545PT Fiches technique(PDF) 10 Page - Texas Instruments |
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TLC320AD545PT Fiches technique(HTML) 10 Page - Texas Instruments |
10 / 35 page 1–4 1.6 Terminal Functions (Continued) TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION DREFP_ADC 47 O ADC voltage reference filter output. DREFP_ADC provides lowpass filtering for the internal bandgap reference. The optimal ceramic capacitor value is 0.1 µF connected between DREFM_ADC and DREFP_ADC. The dc voltage at this terminal is 3.375 V with a 5-V DAVDD supply and 2.25 V with a 3.3-V DAVDD supply. DREFP_DAC 1 O DAC voltage reference filter output. DREFP_DAC provides for lowpass filtering the internal bandgap reference. The optimal ceramic capacitor value is 0.1 µF connected between DREFM_DAC and DREFP_DAC. The dc voltage at this terminal is 3.375 V at 5-V DAVDD supply and 2.25 V at 3.3-V DAVDD supply. DT_BUFM 19 O Buffer amp analog inverting output. DT_BUFM can be programmed for 0 dB, -6 dB, -12 dB, and -18 dB gain or muted using the control registers. This output is normally fed to the DTTX_INM terminal through an input resistor. DT_BUFP 18 O Buffer amp analog noninverting output. DT_BUFP can be programmed for 0 dB, -6 dB, -12 dB and -18 dB gain or muted using the control registers. This output is normally fed to the DTTX_INP terminal through an input resistor. DT_BUFP must be left unconnected in single-ended hybrid. DT_DIN 33 I Digital data input. DT_DIN handles DAC input data as well as control register programming information during frame sync interval and is synchronized to DT_SCLK. DT_DOUT 31 O Digital data output. ADC output bits transmit data during the frame sync period which is synchronized to DT_SCLK. DT_DOUT is at high impedance when DT_FS is not activated. DT_FS 30 O Serial port frame sync signal. DT_FS signals the beginning of transmit for ADC data and receiving of DAC data. This signal can be active high (FS high mode) or active low (FS low mode) depending on the voltage applied to SI_SEL (see Section 4, Serial Communications). DT_MCLK 34 I Master clock input. All internal clocks are derived from this clock. DT_REF 13 O Reference voltage for the transformer at 2.5 V for a 5-V DAVDD supply and 1.5 V for a 3.3-V DAVDD supply. The maximum source or sink current at this terminal is 2.5 mA. DT_REF must be left unconnected in differential hybrid. DTRX_FB 9 O Receive path amplifier feedback node. DTRX_FB terminal is connected to the noninverting output of the receive path amplifier and allows a parallel resistor/capacitor to be placed in the amplifier feedback path for setting gain and filter poles. DTRXM 10 I Receive path amplifier analog inverting input DTRXP 12 I Receive path amplifier analog noninverting input DT_SCLK 32 O Shift clock signal. DT_SCLK clocks serial data into DT_DIN and out of DT_DOUT during the frame-sync interval. DT_SCLK rate is DT_MCLK/2. DTTX_INM 15 I Transmit amplifier analog inverting input. This node is normally fed by the DT_BUFM output through an input resistor. DTTX_INP 16 I Transmit amplifier analog noninverting input. This node is normally fed by the DT_BUFP output through an input resistor. DTTX_INP must be shorted to DTTX_OUTM in single-ended hybrid. DTTX_OUTM 17 O Transmit amplifier analog inverting output. DTTX_OUTM must be shorted to DTTX_INP in single-ended hybrid. DTTX_OUTP 14 O Transmit amplifier analog noninverting output DVDD 22 I Digital and RESET circuit power supply (5 V/3.3 V) DVSS 27 I Digital and RESET circuit ground FILT 46 O Bandgap filter node. FILT provides decoupling of the bandgap reference voltage. This reference is 3.375 V with a 5-V supply and 2.25 V with a 3.3-V supply. The optimal capacitor value is 0.1 µF (ceramic). This node should not be used as a voltage source. FLSH_IN 24 I External ASIC logic input. When brought low, FLSH_IN enables the FLSH_OUT output. FLSH_OUT 23 O Power output to write/erase flash EEPROM device (such as Intel ™ 28F400B or AMD™ Am29F400). Supplies 45 mA maximum from 5 V when FLSH_IN is brought low. MONOUTM 42 O Analog output from 8- Ω monitor speaker amplifier which can be set for 0-dB gain or muted through the control registers. MONOUTP 40 O Analog output from 8- Ω monitor speaker amplifier which can be set for 0-dB gain or muted through the control registers. MVDD 41 I Monitor amplifier supply (5 V/3.3 V) Intel is a trademark of Intel Systems, Inc. AMD is a trademark of Advanced Micro Devices, Inc. |
Numéro de pièce similaire - TLC320AD545PT |
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Description similaire - TLC320AD545PT |
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