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TL16C552AM Fiches technique(PDF) 9 Page - Texas Instruments |
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TL16C552AM Fiches technique(HTML) 9 Page - Texas Instruments |
9 / 39 page TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 transmitter switching characteristics over recommended ranges of operating free-air temperature and supply voltage (see Note 11 and Figures 6, 7, and 8) PARAMETER TEST CONDITIONS MIN MAX UNIT td5 Delay time, interrupt THRE ↓ to SOUT ↓ at start See Figure 6 8 24 RCLK cycles td6 Delay time, SOUT ↓ at start to interrupt THRE ↑ See Note 12 and Figure 6 8 9 RCLK cycles td7 Delay time, IOW (WR THR) ↑ to interrupt THRE ↑ See Note 12 and Figure 6 16 32 RCLK cycles td8 Delay time, SOUT ↓ at start to TXRDY ↓ CL = 100 pF, See Figures 7 and 8 8 RCLK cycles tpd2 Propagation delay time from IOW (WR THR) ↓ to interrupt THRE ↓ CL = 100 pF, See Figure 6 140 ns tpd4 Propagation delay time from IOR (RD IIR) ↑ to interrupt THRE ↓ CL = 100 pF, See Figure 6 140 ns tpd5 Propagation delay time from IOW (WR THR) ↑ to TXRDY ↑ CL = 100 pF, See Figures 7 and 8 195 ns NOTES: 11. These parameters are not production tested. 12. When the transmitter interrupt delay is active, this delay is lengthened by one character time minus the last stop bit time. receiver switching characteristics over recommended ranges of operating free-air temperature and supply voltage (see Note 13 and Figures 9 through 13) PARAMETER TEST CONDITIONS MIN MAX UNIT td9 Delay time from stop to INT ↑ See Note 14 1 RCLK cycle tpd6 Propagation delay time from RCLK ↑ to sample CLK ↑ 100 ns tpd7 Propagation delay time from IOR (RD RBR/RD LSR) ↓ to reset interrupt ↓ CL = 100 pF 150 ns tpd8 Propagation delay time from IOR (RD RBR) ↓ to RXRDY ↑ 150 ns NOTES: 13. These parameters are not production tested. 14. The receiver data available indicator, the overrun error indicator, the trigger level interrupts, and the active RXRDY indicator are delayed three RCLK cycles in FIFO mode (FCR0 = 1). After the first byte has been received, status indicators (PE, FE, BI) are delayed three RCLK cycles. These indicators are updated immediately for any further bytes received after RDRBR goes active. There are eight RCLK cycle delays for trigger change level interrupts. modem control switching characteristics over recommended ranges of operating free-air temperature and supply voltage, CL = 100 pF (see Note 15 and Figure 14) PARAMETER MIN MAX UNIT tpd9 Propagation delay time from IOW (WR MCR) ↑ to RTS (DTR) ↓↑ 100 ns tpd10 Propagation delay time from modem input (CTS, DSR) ↓↑ to interrupt ↑ 170 ns tpd11 Propagation delay time from IOR (RD MSR) ↑ to interrupt ↓ 140 ns tpd12 Propagation delay time from RI ↑ to interrupt ↑ 170 ns NOTE 15: These parameters are not production tested. |
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