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SN75ALS181 Fiches technique(PDF) 5 Page - Texas Instruments |
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SN75ALS181 Fiches technique(HTML) 5 Page - Texas Instruments |
5 / 14 page SN75ALS181 DIFFERENTIAL DRIVER AND RECEIVER PAIR SLLS152B – DECEMBER 1992 – REVISED APRIL 2003 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DRIVER SECTION electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VIK Input clamp voltage II = –18 mA –1.5 V VO Output voltage IO = 0 0 6 V |VOD1| Differential output voltage IO = 0 1.5 6 V VCC = 5 V, 1/2 VOD1 |VOD2| Differential output voltage CC , RL = 100 Ω See Figure 1 2 V RL = 54 Ω 1.5 2.3 5 |VOD3| Differential output voltage Vtest = –7 V to 12 V, See Figure 2 1.5 5 V ∆|VOD| Change in magnitude of differential output voltage (see Note 6) RL = 54 Ω or 100 Ω, See Figure 1 ±0.2 V VOC Common mode output voltage RL =54 Ω or 100 Ω See Figure 1 3 V VOC Common-mode output voltage RL = 54 Ω or 100 Ω, See Figure 1 –1 V ∆|VOC| Change in magnitude of common-mode output voltage (see Note 6) RL = 54 Ω or 100 Ω, See Figure 1 ±0.2 V IOZ High-impedance-state output current VO = –7 V to 12 V, See Note 7 ±100 µA IIH High-level input current VIH = 2.4 V 20 µA IIL Low-level input current VIL = 0.4 V –100 µA VO = –7 V –250 IOS Short circuit output current VO = VCC 250 mA IOS Short-circuit output current VO = 12 V 250 mA VO = 0 V –150 ICC Supply current (total package) No load Outputs enabled 21 30 mA ICC Supply current (total package) No load Outputs disabled 14 21 mA † All typical values are at VCC = 5 V and TA = 25°C. NOTES: 6. ∆|VOD| and ∆|VOC| are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high level to a low level. 7. This applies for both power on and power off. Refer to TIA/EIA-485-A for exact conditions. switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT tdD Differential output delay time, tdDH or tdDL RL = 54 Ω, CL = 50 pF, See Figure 3 9 13 20 ns tsk(p) Pulse skew (|tdDH – tdDL|) RL = 54 Ω, CL = 50 pF, See Figure 3 1 8 ns tt Differential output transition time RL = 54 Ω, CL = 50 pF, See Figure 3 3 10 16 ns tPZH Output enable time to high level RL = 110 Ω, See Figure 4 36 53 ns tPZL Output enable time to low level RL = 110 Ω, See Figure 5 39 56 ns tPHZ Output disable time from high level RL = 110 Ω, See Figure 4 20 31 ns tPLZ Output disable time from low level RL = 110 Ω, See Figure 5 9 20 ns † All typical values are at VCC = 5 V and TA = 25°C. |
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