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SN74GTLP1394PW Fiches technique(PDF) 4 Page - Texas Instruments |
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SN74GTLP1394PW Fiches technique(HTML) 4 Page - Texas Instruments |
4 / 9 page SN74GTLP1394 2-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SELECTABLE POLARITY SCES286 – OCTOBER 1999 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions (see Notes 4 through 6) MIN NOM MAX UNIT VCC, BIAS VCC Supply voltage 3.15 3.3 3.45 V VTT Termination voltage GTL 1.14 1.2 1.26 V VTT Termination voltage GTL+ 1.35 1.5 1.65 V VREF Supply voltage GTL 0.74 0.8 0.87 V VREF Supply voltage GTL+ 0.87 1 1.1 V VI Input voltage B port VTT V VI Input voltage Except B port VCC V B port VREF+0.05 VIH High-level input voltage ERC VCC–0.6 VCC V Except B port and ERC 2 B port VREF–0.05 VIL Low-level input voltage ERC GND 0.6 V Except B port and ERC 0.8 IIK Input clamp current –18 mA IOH High-level output current Y –24 mA IOL Low level output current Y 24 mA IOL Low-level output current B port 100 mA TA Operating free-air temperature –40 85 °C NOTES: 4. All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 5. Normal connection sequence is GND first, BIAS VCC = 3.3 V second, and VCC = 3.3 V, I/O, control inputs, VTT and VREF (any order) last. However, if the B-port I/O precharge is not required, the acceptable connection sequence is GND first and VCC = 3.3 V, BIAS VCC = 3.3 V, I/O, control inputs, VTT and VREF (any order) last. When VCC is connected, the BIAS VCC circuitry is disabled. 6. VTT and RTT can be adjusted to accommodate backplane impedances as long as they do not exceed the DC absolute IOL ratings. Similarly, VREF can be adjusted to optimize noise margins, but normally is 2/3 VTT. |
Numéro de pièce similaire - SN74GTLP1394PW |
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Description similaire - SN74GTLP1394PW |
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