Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN74AVC16373

16-BIT TRANSPARENT D-TYPE LATCH

WITH 3-STATE OUTPUTS

SCES156F – DECEMBER 1998 – REVISED FEBRUARY 2000

1

POST OFFICE BOX 655303

Widebus

™ Family

CMOS) Submicron Process

Dynamically Changes Output Impedance,

Resulting in Noise Reduction Without

Speed Degradation

Mixed-Voltage-Mode Data Communications

Operation

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

JESD 78, Class II

Shrink Small-Outline (DGG) and Thin Very

Small-Outline (DGV) Packages

description

A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output

impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1

circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is

equivalent to a high-drive standard-output device. For more information, refer to the TI application reports,

AVC

Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC

™)

Circuitry Technology and Applications, literature number SCEA009.

136

–128

–144

–160

0.4

0.8

1.2

1.6

2.0

2.4

2.8

170

153

119

102

85

68

51

34

17

0

0.4

0.8

1.2

1.6

2.0

2.4

2.8

3.2

TA = 25°C

Process = Nominal

IOL – Output Current – mA

VCC = 3.3 V

VCC = 2.5 V

VCC = 1.8 V

TA = 25°C

Process = Nominal

IOH – Output Current – mA

VCC = 3.3 V

VCC = 2.5 V

VCC = 1.8 V

–80

–96

–112

–32

–48

–64

0

–16

Figure 1. Output Voltage vs Output Current

The SN74AVC16373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus

drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the

latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs

are latched at the levels set up at the D inputs.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Copyright

© 2000, Texas Instruments Incorporated

DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.