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SN74ALVCH16825DGG Fiches technique(PDF) 1 Page - Texas Instruments |
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SN74ALVCH16825DGG Fiches technique(HTML) 1 Page - Texas Instruments |
1 / 8 page SN74ALVCH16825 18-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES039C – JULY 1995 – REVISED FEBRUARY 1999 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Member of the Texas Instruments Widebus ™ Family D EPIC ™ (Enhanced-Performance Implanted CMOS) Submicron Process D ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) D Latch-Up Performance Exceeds 250 mA Per JESD 17 D Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors D Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages description This 18-bit buffer and line driver is designed for 1.65-V to 3.6-V VCC operation. This SN74ALVCH16825 improves the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used as two 9-bit buffers or one 18-bit buffer. It provides true data. The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1 or OE2) input is high, all nine affected outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating inputs at a valid logic level. The SN74ALVCH16825 is characterized for operation from –40 °C to 85°C. FUNCTION TABLE (each 9-bit section) INPUTS OUTPUT OE1 OE2 A Y L L L L L LH H H XX Z X H X Z Copyright © 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DGG OR DL PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1OE1 1Y1 1Y2 GND 1Y3 1Y4 VCC 1Y5 1Y6 1Y7 GND 1Y8 1Y9 GND GND 2Y1 2Y2 GND 2Y3 2Y4 2Y5 VCC 2Y6 2Y7 GND 2Y8 2Y9 2OE1 1OE2 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 1A7 GND 1A8 1A9 GND GND 2A1 2A2 GND 2A3 2A4 2A5 VCC 2A6 2A7 GND 2A8 2A9 2OE2 EPIC and Widebus are trademarks of Texas Instruments Incorporated. |
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