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SN74ACT3631 Fiches technique(PDF) 10 Page - Texas Instruments

No de pièce SN74ACT3631
Description  512 횞 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

SN74ACT3631 Fiches technique(HTML) 10 Page - Texas Instruments

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SN74ACT3631
512
× 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246G – AUGUST 1993 – REVISED APRIL 1998
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Two low-to-high transitions of CLKA are required after a FIFO read for its almost-full flag to reflect the new level
of fill; therefore, the almost-full flag of a FIFO containing [512 – (Y + 1)] or fewer words remains low if two cycles
of CLKA have not elapsed since the read that reduced the number of words in memory to [512 – (Y + 1)]. An
almost-full flag is set high by the second low-to-high transition of CLKA after the FIFO read that reduces the
number of words in memory to [512 – (Y + 1)]. A low-to-high transition of CLKA begins the first synchronization
cycle if it occurs at time tsk(2), or greater, after the read that reduces the number of words in memory to
[512 – (Y + 1)]. Otherwise, the subsequent CLKA cycle can be the first synchronization cycle (see Figure 9).
synchronous retransmit
The synchronous-retransmit feature of the SN74ACT3631 allows FIFO data to be read repeatedly starting at
a user-selected position. The FIFO is first put into retransmit mode to select a beginning word and prevent
ongoing FIFO write operations from destroying retransmit data. Data vectors with a minimum length of three
words can retransmit repeatedly starting at the selected word. The FIFO can be taken out of retransmit mode
at any time and allow normal device operation.
The FIFO is put in retransmit mode by a low-to-high transition on CLKB when the retransmit-mode (RTM) input
is high and OR is high. This rising CLKB edge marks the data present in the FIFO output register as the first
retransmit data. The FIFO remains in retransmit mode until a low-to-high transition occurs while RTM is low.
When two or more reads occur after the initial retransmit word, a retransmit is initiated by a low-to-high transition
on CLKB when the read-from-mark (RFM) input is high. This rising CLKB edge shifts the first retransmit word
to the FIFO output register and subsequent reads can begin immediately. Retransmit loops can be done
endlessly while the FIFO is in retransmit mode. RFM must be low during the CLKB rising edge that takes the
FIFO out of retransmit mode.
When the FIFO is put into retransmit mode, it operates with two read pointers. The current read pointer operates
normally, incrementing each time a new word is shifted to the FIFO output register and used by the OR and AE
flags. The shadow read pointer stores the SRAM location at the time the device is put into retransmit mode and
does not change until the device is taken out of retransmit mode. The shadow read pointer is used by the IR
and AF flags. Data writes can proceed while the FIFO is in retransmit mode, but AF is set low by the write that
stores (512 – Y) words after the first retransmit word. The IR flag is set low by the 512th write after the first
retransmit word.
When the FIFO is in retransmit mode and RFM is high, a rising CLKB edge loads the current read pointer with
the shadow read-pointer value and the OR flag reflects the new level of fill immediately. If the retransmit changes
the FIFO status out of the almost-empty range, up to two CLKB rising edges after the retransmit cycle are
needed to switch AE high (see Figure 11). The rising CLKB edge that takes the FIFO out of retransmit mode
shifts the read pointer used by the IR and AF flags from the shadow to the current read pointer. If the change
of read pointer used by IR and AF should cause one or both flags to transition high, at least two CLKA
synchronizing cycles are needed before the flags reflect the change. A rising CLKA edge after the FIFO is taken
out of retransmit mode is the first synchronizing cycle of IR if it occurs at time tsk(1), or greater, after the rising
CLKB edge (see Figure 12). A rising CLKA edge after the FIFO is taken out of retransmit mode is the first
synchronizing cycle of AF if it occurs at time tsk(2), or greater, after the rising CLKB edge (see Figure 14).
mailbox registers
Two 36-bit bypass registers pass command and control information between port A and port B. The
mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data transfer operation.
A low-to-high transition on CLKA writes A0 – A35 data to the mail1 register when a port-A write is selected by
CSA, W/RA, and ENA with MBA high. A low-to-high transition on CLKB writes B0 – B35 data to the mail2 register
when a port-B write is selected by CSB, W/RB, and ENB with MBB high. Writing data to a mail register sets its
corresponding flag (MBF1 or MBF2) low. Attempted writes to a mail register are ignored while its mail flag is
low.


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