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SN74LV240APWLE Fiches technique(PDF) 2 Page - Texas Instruments |
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SN74LV240APWLE Fiches technique(HTML) 2 Page - Texas Instruments |
2 / 15 page SN54LV240A, SN74LV240A OCTAL BUFFERS/DRIVERS WITH 3STATE OUTPUTS SCLS384H − SEPTEMBER 1997 − REVISED APRIL 2005 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description/ordering information (continued) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE (each buffer) INPUTS OUTPUT OE A OUTPUT Y L H L L LH H X Z logic diagram (positive logic) 1 218 1Y1 1OE 1A1 416 1Y2 1A2 614 1Y3 1A3 812 1Y4 1A4 19 11 9 2Y1 2OE 2A1 13 7 2Y2 2A2 15 5 2Y3 2A3 17 3 2Y4 2A4 |
Numéro de pièce similaire - SN74LV240APWLE |
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Description similaire - SN74LV240APWLE |
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