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CDK3402CTQ48 Fiches technique(PDF) 7 Page - Cadeka Microcircuits LLC.

No de pièce CDK3402CTQ48
Description  8-bit, 100/150MSPS, Triple Video DACs
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Fabricant  CADEKA [Cadeka Microcircuits LLC.]
Site Internet  http://www.cadeka.com
Logo CADEKA - Cadeka Microcircuits LLC.

CDK3402CTQ48 Fiches technique(HTML) 7 Page - Cadeka Microcircuits LLC.

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7
Data Sheet
Current-Setting Resistor - RREF
Full-scale output current of each D/A converter is deter-
mined by the value of the resistor connected between
RREF and GND. Nominal value of RREF is found from:
RREF = 9.1 (VREF/IFS)
where IFS is the full-scale (white) output current (in amps)
from the D/A converter (without sync). Sync is 0.4 * IFS.
D/A full-scale (white) current may also be calculated from:
IFS = VFS/RL
Where VFS is the white voltage level and RL is the total
resistive load (Ω) on each D/A converter. VFS is the blank
to full-scale voltage.
Voltage Reference
All three D/A converters are supplied with a common
voltage reference. Internal bandgap voltage reference
voltage is +1.235V with a 3kΩ source resistance. An
external voltage reference may be connected to the VREF
pin, overriding the internal voltage reference.
A 0.1µF capacitor must be connected between the COMP
pin and VDD to stabilize internal bias circuitry and ensure
low-noise operation.
Voltage Reference Output/Input - VREF
An internal voltage source of +1.235V is output on the
VREF pin. An external +1.235V reference may be applied
here which overrides the internal reference. Decoupling
VREF to GND with a 0.1µF ceramic capacitor is required.
Power and Ground
Required power is a single +5.0V supply. To minimize power
supply induced noise, analog +5V should be connected
to VDD pins with 0.1µF and 0.01µF decoupling capacitors
placed adjacent to each VDD pin or pin pair.
The high slew-rate of digital data makes capacitive cou-
pling to the outputs of any D/A converter a potential
problem. Since the digital signals contain high-frequency
components of the CLK signal, as well as the video out-
put signal, the resulting data feedthrough often looks
like harmonic distortion or reduced signal-to-noise perfor-
mance. All ground pins should be connected to a common
solid ground plane for best performance.


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