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CDK2307AILP64X Fiches technique(PDF) 3 Page - Cadeka Microcircuits LLC. |
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CDK2307AILP64X Fiches technique(HTML) 3 Page - Cadeka Microcircuits LLC. |
3 / 16 page ©2009 CADEKA Microcircuits LLC www.cadeka.com 3 Data Sheet Pin No. Pin Name Description 19 CLK_EXT_EN CLK_EXT signal enabled when low (zero). Tristate when high. 20 DFRMT Data format selection. 0: Offset Binary, 1: Two's Complement 21 PD_N Full chip Power Down mode when Low. All digital outputs reset to zero. After chip power up, always apply Power Down mode before using Active Mode to reset chip. 22 OE_N_1 Output Enable Channel 0. Tristate when high. 24, 41, 58 OVDD I/O ring post-driver supply voltage. Voltage range 1.7V to 3.6V. 25, 40, 57 OVSS Ground for I/O ring 26 D1_0 Output Data Channel 1 (LSB, 13-bit output or 1Vpp full scale range ) 27 D1_1 Output Data Channel 1 (LSB, 12-bit output 2Vpp full scale range) 28 D1_2 Output Data Channel 1 29 D1_3 Output Data Channel 1 30 D1_4 Output Data Channel 1 31 D1_5 Output Data Channel 1 32 D1_6 Output Data Channel 1 33 D1_7 Output Data Channel 1 34 D1_8 Output Data Channel 1 35 D1_9 Output Data Channel 1 36 D1_10 Output Data Channel 1 37 D1_11 Output Data Channel 1 (MSB for 1Vpp full scale range, see Reference Voltages section) 38 D1_12 Output Data Channel 1 (MSB for 2Vpp full scale range) 39 ORNG_1 Out of Range flag Channel 1. High when input signal is out of range 42 CLK_EXT Output clock signal for data synchronization. CMOS levels. 43 D0_0 Output Data Channel 0 (LSB, 13 bit output or 1Vpp full scale range) 44 D0_1 Output Data Channel 0 (LSB, 12 bit output 2Vpp full scale range) 45 D0_2 Output Data Channel 0 46 D0_3 Output Data Channel 0 47 D0_4 Output Data Channel 0 48 D0_5 Output Data Channel 0 49 D0_6 Output Data Channel 0 50 D0_7 Output Data Channel 0 51 D0_8 Output Data Channel 0 52 D0_9 Output Data Channel 0 53 D0_10 Output Data Channel 0 54 D0_11 Output Data Channel 0 (MSB for 1Vpp full scale range, see Reference Voltages section) 55 D0_12 Output Data Channel 0 (MSB for 2Vpp full scale range) 56 ORNG_0 Out of Range flag Channel 0. High when input signal is out of range. 59 OE_N_0 Output Enable Channel 0. Tristate when low. 60, 61 CM_EXTBC_1, CM_EXTBC_0 Bias control bits for the buffer driving pin CM_EXT 00: Off 10: 50uA 10: 500uA 11: 1mA 62, 63 SLP_N_1, SLP_N_0 Sleep Mode 00: Sleep Mode 01: Channel 0 active 10: Channel 1 active 11: Both channels active Pin Assignments (Continued) |
Numéro de pièce similaire - CDK2307AILP64X |
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Description similaire - CDK2307AILP64X |
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