©2008 CADEKA Microcircuits LLC

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2

Data Sheet

Pin Configuration

TQFP-44

CDK1301

Pin Assignments

Pin No.

Pin Name

Description

40

39

16-9

Data output bank A; 3V/5V LVCMOS compatible

19-26

Data output bank B; 3V/5V LVCMOS compatible

28

Non-inverted data output clock; 3v/5v 3V/5V LVCMOS compatible

27

Inverted data output clock; 3V/5V LVCMOS compatible

4

CLK

Non-inverted clock input pin; 100k pulldown to AGND, internally

3

CLK

5

RESET

RESET synchronizes the data sampling and data output bank relationship when in dual channel

6

RESET

32, 31

2

PD

Power-Down pin; PD = 1 for Power-Down mode. Outputs set to high impedance in Power-Down

mode; 100k pulldown to AGND, internally

37

2.5V common mode voltage reference output

35, 36,

42, 43

+5V analog supply

7, 17, 30

+3V/+5V digital output supply

1, 33, 34,

38, 41, 44

AGND

Analog ground

8, 18, 29

DGND

Digital ground