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SN74ACT8997NT Fiches technique(PDF) 10 Page - Texas Instruments

No de pièce SN74ACT8997NT
Description  SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES SCAN-CONTROLLED IEEE STD 1149.1 JTAG TAP CONCATENATORS
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

SN74ACT8997NT Fiches technique(HTML) 10 Page - Texas Instruments

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SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D – APRIL 1990 – REVISED DECEMBER 1996
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
control register description
The control register (CTLR) is a 10-bit serial register that controls the enable and select functions of the
’ACT8997. A reset operation forces all bits to a low logic level. The contents of the CTLR are latched and
decoded during the Update-DR TAP state. The specific function of each bit is listed in Table 5. The enable and
select functions of the CTLR bits are mapped as follows:
Table 5. Control-Register Bit Mapping
BIT
VALUE
FUNCTION
9
0
Configure counter to count up
9
1
Configure counter to count down
8
0
Do not stop counting when the count reaches 00000000
8
1
Stop counting when the count reaches 00000000 (count down only)
7
0
Configure DCO as an active-low output
7
1
Configure DCO as an active-high output
00
DCO = Inactive (level depends on CTLR bit 7)
65
01
DCO = IRERR
6, 5
10
DCO = CE, an internal logic 0 generated when the count is 00000000 (count down) or 11111111 (count up)
11
DCO = DCI
4
0
Do not mask IRERR from DCO
4
1
Mask IRERR from DCO
3
0
Configure DCO as an open-drain output
3
1
Configure DCO as a 3-state output
2
0
Disable DCO
2
1
Enable DCO
1
0
Configure DCI as an active-low input
1
1
Configure DCI as an active-high input
0
0
Enable DTCK, DTDO(1–4), and DTMS(1–4) [outputs DTDO(1–4) depend on select register (see Table 7)]
0
1
Disable DTCK, DTDO(1–4), and DTMS(1–4)
Bit 9 – Up/Down
This bit sets the count mode of the counter register (reset condition = count up).
Bit 8 – Latch on Zero
The counter register can be configured to stop counting when its value is 00000000 and ignore subsequent
transitions on the counter clock, DCI. The latch-on-zero option is valid only in the count-down mode
(reset condition = do not latch on zero). The value of this bit has no effect on the operation of the counter if
CTLR bit 9 = 0.
Bit 7 – DCO Polarity Select
DCO can be configured as an active-low or active-high output (reset condition = active low).
Bit 6/Bit 5 – DCO Source Select 1/DCO Source Select 0
DCO can be used to output the IRERR signal generated by the ’ACT8997 (see Table 3). Bits 6 and 5 can be
set to output IRERR via DCO on the falling edge of TCK in the Pause-IR state. DCO can also be configured
to become active when the value of the counter is 00000000, to follow DCI, or be set to a static high or low level
(reset condition = static high level).


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