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SN74ABT18504PM Fiches technique(PDF) 3 Page - Texas Instruments |
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SN74ABT18504PM Fiches technique(HTML) 3 Page - Texas Instruments |
3 / 30 page SN54ABT18504, SN74ABT18504 SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS108B – AUGUST 1992 – REVISED JUNE 1993 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 description (continued) Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry can perform other testing functions such as parallel signature analysis on data inputs and pseudo-random pattern generation from data outputs. All testing and scan operations are synchronized to the TAP interface. Additional flexibility is provided in the test mode through the use of two boundary scan cells (BSCs) for each I/O pin. This allows independent test data to be captured and forced at either bus (A or B). A PSA/COUNT instruction is also included to ease the testing of memories and other circuits where a binary count addressing scheme is useful. The SN54ABT18504 is characterized for operation over the full military temperature range of – 55 °C to 125°C. The SN74ABT18504 is characterized for operation from – 40 °C to 85°C. FUNCTION TABLE† (normal mode, each register) INPUTS OUTPUT OEAB LEAB CLKENAB CLKAB A B L L L L X B0‡ L LL ↑ LL L LL ↑ HH L LH X X B0‡ L HX X L L L HX X H H H X X X X Z † A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKENBA, and CLKBA. ‡ Output level before the indicated steady-state input conditions were established. |
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