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CD74HC597 Datasheet(Fiches technique) 7 Page - Texas Instruments

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Numéro de pièce CD74HC597
Description  High Speed CMOS Logic 8-Bit Shift Register with Input Storage
Télécharger  10 Pages
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
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 7 page
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7
MR to Q7
tPLH, tPHL
CL = 50pF
4.5
-
-
44
-
55
-
66
ns
CL = 15pF
5
-
18
-
-
-
-
-
ns
Output Transition Time
tTLH, tTHL
CL = 50pF
4.5
-
-
15
-
19
-
22
ns
Input Capacitance
CI
CL = 50pF
-
-
-
10
-
10
-
10
pF
Power Dissipation
Capacitance, (Notes 4, 5)
CPD
-
5
-
18.5
-
-
-
-
-
pF
NOTES:
4. CPD is used to determine the dynamic power consumption, per package.
5. PD =CPD VCC
2 f
i + Σ (CL VCC
2 f
o) where: fi = Input Frequency, fo = Output Frequency, CL = Output Load Capacitance, VCC = Supply
Voltage.
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
VCC (V)
25oC
-40oCto85oC -55oC to 125oC
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
Test Circuits and Waveforms
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 3. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
CLOCK
90%
50%
10%
GND
VCC
trCL
tfCL
50%
50%
tWL
tWH
10%
tWL + tWH =
fCL
I
CLOCK
2.7V
1.3V
0.3V
GND
3V
trCL = 6ns
tfCL = 6ns
1.3V
1.3V
tWL
tWH
0.3V
tWL + tWH =
fCL
I
tPHL
tPLH
tTHL
tTLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
VCC
tr = 6ns
tf = 6ns
90%
tPHL
tPLH
tTHL
tTLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
tr = 6ns
tf = 6ns
90%
CD74HC597, CD74HCT597




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Numéro de composants électroniques

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