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CD74HC173 Datasheet(Fiches technique) 1 Page - Texas Instruments

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Numéro de pièce CD74HC173
Description  High Speed CMOS Logic Quad D-Type Flip-Flop, Three-State
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
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1
Data sheet acquired from Harris Semiconductor
SCHS158
Features
• Three-State Buffered Outputs
• Gated Input and Output Enables
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
Pinout
CD74HC173, CD74HC173
(PDIP, SOIC)
TOP VIEW
Description
The Harris CD74HC173 and CD74HCT173 high speed
three-state quad D-type flip-flops are fabricated with silicon
gate CMOS technology. They possess the low power con-
sumption of standard CMOS Integrated circuits, and can
operate at speeds comparable to the equivalent low power
Schottky devices. The buffered outputs can drive 15 LSTTL
loads. The large output drive capability and three-state fea-
ture make these parts ideally suited for interfacing with bus
lines in bus oriented systems.
The four D-type flip-flops operate synchronously from a com-
mon clock. The outputs are in the three-state mode when
either of the two output disable pins are at the logic “1” level.
The input ENABLES allow the flip-flops to remain in their
present states without having to disrupt the clock If either of
the 2 input ENABLES are taken to a logic “1” level, the Q
outputs are fed back to the inputs, forcing the flip-flops to
remain in the same state. Reset is enabled by taking the
MASTER RESET (MR) input to a logic “1” level. The data
outputs change state on the positive going edge of the clock.
The CD74HCT173 logic family is functionally, as well as pin
compatible with the standard 74LS logic family
.
OE
OE2
Q0
Q1
Q2
Q3
GND
VCC
MR
D0
D1
D2
D3
E2
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
E1
CP
Ordering Information
PART NUMBER
TEMP. RANGE
(oC)
PACKAGE
PKG.
NO.
CD74HC173E
-55 to 125
16 Ld PDIP
E16.3
CD74HCT173E
-55 to 125
16 Ld PDIP
E16.3
CD74HC173M
-55 to 125
16 Ld SOIC
M16.15
CD74HCT173M
-55 to 125
16 Ld SOIC
M16.15
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
February 1998
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1998
CD74HC173,
CD74HCT173
High Speed CMOS Logic
Quad D-Type Flip-Flop, Three-State
File Number
1641.1
[ /Title
(CD74H
C173,
CD74H
CT173)
/Subject
(High
Speed
CMOS
Logic
Quad D-
Type




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