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MC-ACT-UL3LINK-NET Fiches technique(PDF) 3 Page - Actel Corporation

No de pièce MC-ACT-UL3LINK-NET
Description  Function compatible with ATM Forum Asynchronous/synchronous FIFO using RAM
Download  5 Pages
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Fabricant  ACTEL [Actel Corporation]
Site Internet  http://www.actel.com
Logo ACTEL - Actel Corporation

MC-ACT-UL3LINK-NET Fiches technique(HTML) 3 Page - Actel Corporation

  MC-ACT-UL3LINK-NET Datasheet HTML 1Page - Actel Corporation MC-ACT-UL3LINK-NET Datasheet HTML 2Page - Actel Corporation MC-ACT-UL3LINK-NET Datasheet HTML 3Page - Actel Corporation MC-ACT-UL3LINK-NET Datasheet HTML 4Page - Actel Corporation MC-ACT-UL3LINK-NET Datasheet HTML 5Page - Actel Corporation  
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Device Requirements
Family
Device
Utilization
Performance
COMB
SEQ
Tiles
Axcelerator
AX250
38%
76%
n/a
104 MHz
ProASIC3
A3PE600
n/a
n/a
20%
97 MHz
ProASICPLUS
APA150
n/a
n/a
53%
85 MHz
Table 1: Device Utilization and Performance
Verification and Compliance
The testbench is self-checking, which means that if there is an error detected in the start word, end word, or payload the testbench will assert one or both of two error
signals. The test checks for errors at two stages in the testbench: when the cells (packets) are looped back through the PHY device (SIG_LOOP_ERROR_OUT), and
upon reading out of the link device (SIG_ERROR_OUT). This core has also been used successfully in customer designs.
Signal Descriptions
The following signal descriptions define the IO signals.
Signal
Width
Direction
Description
WR_ENB
N
Input
Write enable signal for FIFO
WR_DATA
N*8/16/32
Input
Write data bus for FIFO
WR_FLAG
N
Output
Write flag indicating if FIFO can accept another cell
WR_CLK
N
Input
Write clock for the FIFO
RESET_N
1
Input
Reset signal from user logic
RD_ENB
N
Input
Read enable signal for the FIFO
RD_DATA
N*8/16/32
Output
Read data bus for the FIFO
RD_FLAG
N
Output
FIFO read flag indicating that a cell is ready to be read from the ports FIFO
RD_CLK
N
Input
Read clock for the FIFO
TXCLK
1
Input
Tx utopia clock
TX_DATA
8/16/32
Output
Tx utopia data bus
TXENB_N
1
Output
Tx utopia enable signal
TXCLAV
1/N<4
Input
Tx utopia cell available signal(s)
TX_SOC
1
Output
Tx utopia start of cell signal
TXPRTY
1
Output
Tx utopia parity signal
TX_ADDR
8
Output
Tx utopia polling address bus
RXCLK
1
Input
Ingress utopia clock
RXDATA
8/16/32
Input
Ingress utopia data bus
RXENB_N
1
Output
Ingress utopia enable signal
RX_CLAV
1/ N<4
Input
Ingress utopia cell available signal(s)
RX_PRTY
1
Input
Ingress utopia parity signal
RX_SOC
1
Input
Ingress utopia start of cell signal
RX_ADDR
8
Output
Ingress utopia address bus
Table 2: Core I/O Signals


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