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TLC5926 Fiches technique(PDF) 11 Page - Texas Instruments |
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TLC5926 Fiches technique(HTML) 11 Page - Texas Instruments |
11 / 29 page Switching Characteristics TLC5926, TLC5927 www.ti.com ....................................................................................................................................................................................................... SLVS677 – JULY 2008 VDD = 5.5 V, TJ = –40°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH1 Low-to-high propagation delay time, CLK to OUTn 27 65 95 ns tPLH2 Low-to-high propagation delay time, LE(ED1) to OUTn 27 65 95 ns tPLH3 Low-to-high propagation delay time, OE(ED2) to OUTn 27 65 95 ns tPLH4 Low-to-high propagation delay time, CLK to SDO 20 30 ns tPHL1 High-to-low propagation delay time, CLK to OUTn 180 300 445 ns tPHL2 High-to-low propagation delay time, LE(ED1) to OUTn 180 300 445 ns tPHL3 High-to-low propagation delay time, OE(ED2) to OUTn 180 300 445 ns tPHL4 High-to-low propagation delay time, CLK to SDO 20 30 ns tw(CLK) Pulse duration, CLK 20 ns VIH = VDD, VIL = GND, tw(L) Pulse duration LE(ED1) 20 ns Rext = 360 Ω, VL = 4 V, tw(OE) Pulse duration, OE(ED2) 1000 ns RL = 44 Ω, CL = 70 pF, tw(ED2) Pulse duration, OE(ED2) in Error Detection mode 2 µs CG = 0.992 th(ED1,ED2) Hold time, LE(ED1), and OE(ED2) 10 ns th(D) Hold time, SDI 3 ns tsu(D,ED1,ED2) Setup time, SDI, LE(ED1), and OE(ED2) 4 ns th(L) Hold time, LE(ED1), Normal mode 15 ns tsu(L) Setup time, LE(ED1), Normal mode 15 ns tr Rise time, CLK(1) 500 ns tf Fall time, CLK(1) 500 ns tor Rise time, outputs (off) 245 ns tof Rise time, outputs (on) 570 ns fCLK Clock frequency Cascade operation 30 MHz (1) If the devices are connected in cascade and tr or tf is large, it may be critical to achieve the timing required for data transfer between two cascaded devices. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): TLC5926 TLC5927 |
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