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TLC5926 Fiches technique(PDF) 7 Page - Texas Instruments |
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TLC5926 Fiches technique(HTML) 7 Page - Texas Instruments |
7 / 29 page Recommended Timing TLC5926, TLC5927 www.ti.com ....................................................................................................................................................................................................... SLVS677 – JULY 2008 VDD = 3 V to 5.5 V (unless otherwise noted) TEST CONDITIONS MIN MAX UNIT tw(L) LE(ED1) pulse duration Normal mode 20 ns tw(CLK) CLK pulse duration Normal mode 20 ns tw(OE) OE(ED2) pulse duration Normal mode 1000 ns tsu(D) Setup time for SDI Normal mode 7 ns th(D) Hold time for SDI Normal mode 3 ns tsu(L) Setup time for LE(ED1) Normal mode 18 ns th(L) Hold time for LE(ED1) Normal mode 18 ns tw(CLK) CLK pulse duration Error Detection mode 20 ns tw(ED2) OE(ED2) pulse duration Error Detection mode 2000 ns tsu(ED1) Setup time for LE(ED1) Error Detection mode 7 ns th(ED1) Hold time for LE(ED1) Error Detection mode 10 ns tsu(ED2) Setup time for OE(ED2) Error Detection mode 7 ns th(ED2) Hold time for OE(ED2) Error Detection mode 10 ns fCLK Clock frequency Cascade operation, VDD = 3 V to 5.5 V 30 MHz Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): TLC5926 TLC5927 |
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Description similaire - TLC5926 |
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