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ISL32274EFBZ Fiches technique(PDF) 8 Page - Intersil Corporation |
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ISL32274EFBZ Fiches technique(HTML) 8 Page - Intersil Corporation |
8 / 20 page 8 FN6824.0 December 16, 2008 Driver Disable from Output High tHZ SW = GND (see Figure 3) Full - - 20 ns Driver Disable from Output Low tLZ SW = VCC (see Figure 3) Full - - 20 ns Driver Enable from SHDN to High tSDH ISL32179E Only, SW = GND (see Figure 3, Note 13) Full - - 750 ns Driver Enable from SHDN to Low tSDL ISL32179E Only, SW = VCC (see Figure 3, Note 13) Full - - 750 ns DRIVER SWITCHING CHARACTERISTICS (ISL32172E, ISL32174E, ISL32179E, 32Mbps) Maximum Data Rate fMAX VOD = ±1.5V, CD = 100pF (see Figure 4) Full 32 50 - Mbps Driver Single-Ended Output Delay tPLH, tPHL RDIFF = 100Ω, CD = 50pF (see Figure 2) Full 3 8 15 ns Driver Single-Ended Output Skew tSSK RDIFF = 100Ω, CD = 50pF (see Figure 2) Full - 1 3.5 ns Ch-to-Ch Output Delay Skew tSKCC (Figure 2, Note 11) Full - 3 5.5 ns Part-to-Part Output Delay Skew tSKPP (Figure 2, Note 8) Full - - 8 ns Driver Differential Output Skew tDSK RDIFF = 100Ω, CD = 50pF (see Figure 2) Full - 0.5 2 ns Driver Differential Rise or Fall Time tR, tF RDIFF = 100Ω, CD = 50pF (see Figure 2) Full - 7 12 ns Driver Enable to Output High tZH SW = GND (see Figure 3, Note 12) Full - - 20 ns Driver Enable to Output Low tZL SW = VCC (see Figure 3, Note 12) Full - - 20 ns Driver Disable from Output High tHZ SW = GND (see Figure 3) Full - - 20 ns Driver Disable from Output Low tLZ SW = VCC (see Figure 3) Full - - 20 ns Driver Enable from SHDN to High tSDH ISL32179E Only, SW = GND (see Figure 3, Note 13) Full - - 750 ns Driver Enable from SHDN to Low tSDL ISL32179E Only, SW = VCC (see Figure 3, Note 13) Full - - 750 ns NOTES: 6. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. 7. Applies to peak current. See “Typical Performance Curves” beginning on page 12 for more information. 8. tSKPP is the magnitude of the difference in propagation delays of the specified terminals of two units tested with identical test conditions (VCC, temperature, etc.). 9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 10. EN = 0 indicates that the output(s) under test are disabled via the appropriate logic pin settings. EN = 1 indicates that the logic pins are set to enable the output(s) under test. 11. Channel-to-channel skew is the magnitude of the worst case delta between any two propagation delays of any two outputs on the same IC, at the same test conditions. 12. For ISL32179E, keep SHDNEN low to avoid entering SHDN. 13. Keep SHDNEN high to enter SHDN when all transmitters are disabled (ISL32179E only). 14. Logic Pins are the DIs, the enable variants, and SHDNEN. 15. Only one of the SPX pins low, plus EN1-EN4 low with EN and EN high, or EN low and EN high with EN1-EN4 high. 16. Temperature range is -20°C to +40°C. Electrical Specifications Test Conditions: VCC = 3.0V to 3.6V and 4.5V to 5.5V; VL = VCC (ISL32179E only); Typicals are at VCC = 3.3V or VCC = 5V, TA = +25°C; Unless Otherwise Specified.(Notes 6, 10) (Continued) PARAMETER SYMBOL TEST CONDITIONS TEMP (°C) MIN (Note 9) TYP MAX (Note 9) UNITS ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E |
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